DF2218BR24V Renesas Electronics America, DF2218BR24V Datasheet - Page 508

• Manufacturer Part Number: DF2218BR24V
• Description: IC H8S/2218 MCU FLASH 112-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2218BR24V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: SCI, SmartCard, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-LFBGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW3DK2218 - DEV EVAL KIT H8S/2218
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

13.3
The boundary scan function has the following registers. These registers cannot be accessed by the
CPU.
• Instruction register (INSTR)
• IDCODE register (IDCODE)
• BYPASS register (BYPASS)
• Boundary scan register (BSCANR)
13.3.1
INSTR is a 3-bit register. At initialization, this register is specified to IDCODE mode. When
TRST is pulled low, or when the TAP controller is in the Test-Logic-Reset state, INSTR is
initialized. INSTR can be written by the serial data input from the TDI. If more than three bits of
instruction is input from the TDI, INSTR stores the last three bits of serial data.
If a command reserved in INSTR is used, the correct operation cannot be guaranteed.
Table 13.2 Instruction Configuration
Rev.7.00 Dec. 24, 2008 Page 452 of 698
REJ09B0074-0700
Bit
2
1
0
Bit 2
TI2
0
0
0
0
1
1
1
1
Bit Name
TI2
TI1
TI0
Instruction Register (INSTR)
Register Descriptions
Bit1
TI1
0
0
1
1
0
0
1
1
Initial Value R/W
1
0
1
Bit 0
TI0
0
1
0
1
0
1
0
1
Instruction
EXTEST
SAMPLE/PRELOAD
CLAMP
HIGHZ
Reserved
IDCODE (initial value)
Reserved
BYPASS
—
—
—
Test Instruction Bits
Instruction configuration is shown in table 13.2.
Description