DF2218BR24V Renesas Electronics America, DF2218BR24V Datasheet - Page 567

IC H8S/2218 MCU FLASH 112-LFBGA

DF2218BR24V

Manufacturer Part Number
DF2218BR24V
Description
IC H8S/2218 MCU FLASH 112-LFBGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheets

Specifications of DF2218BR24V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
24MHz
Connectivity
SCI, SmartCard, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
112-LFBGA
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW3DK2218 - DEV EVAL KIT H8S/2218
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2218BR24V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
(5) Status Stage (Control-Out)
The control-out status stage starts with an IN token from the host. When an IN-token is
received at the start of the status stage, there is not yet any data in the EP0i FIFO, and so an
EP0i transfer request interrupt is generated. The firmware recognizes from this interrupt that
the status stage has started. Next, in order to transmit 0-byte data to the host, 1 is written to the
EP0i packet enable bit but no data is written to the EP0i FIFO. As a result, the next IN token
causes 0-byte data to be transmitted to the host, and control transfer ends.
After the firmware has finished all processing relating to the data stage, 1 should be written to
the EP0i packet enable bit.
Transfer 0-byte data to host
(EP0iTS in UIFR0 = 1)
End of control transfer
Receive IN token
Set EP0i transmit
in EP0i FIFO?
complete flag
Valid data
USB function
Figure 14.16 Status Stage Operation (Control-Out)
Yes
ACK
No
NAK
EXIRQx
EXIRQx
Rev.7.00 Dec. 24, 2008 Page 511 of 698
request interrupt enable bit
(EP0iPKTE in UTRG0 = 1)
(EP0iTRE in UIER0 = 0)
Write 0 to EP0i transfer
(EP0iTR in UIFR0 = 0)
Write 1 to EP0i packet
(EP0iTS in UIFR0 = 0)
End of control transfer
Clear EP0i transmit
Clear EP0i transfer
Firmware
complete flag
request flag
enable bit
REJ09B0074-0700

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