DF2218BR24V Renesas Electronics America, DF2218BR24V Datasheet - Page 541

• Manufacturer Part Number: DF2218BR24V
• Description: IC H8S/2218 MCU FLASH 112-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2218BR24V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: SCI, SmartCard, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-LFBGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW3DK2218 - DEV EVAL KIT H8S/2218
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14.3.20 USB Interrupt Enable Register 1 (UIER1)
UIER1 enables the interrupt request indicated in the interrupt flag register 1 (UIFR1). When an
interrupt flag is set while the corresponding bit in UIER1 is set to 1, an interrupt is requested by
asserting the corresponding EXIRQ0 or EXIRQ1. Either EXIRQ0 or EXIRQ1 must be selected by
the interrupt select register 1 (UISR1).
14.3.21 USB Interrupt Enable Register 3 (UIER3)
UIER3 enables the interrupt request indicated in the interrupt flag register 3 (UIFR3). This register
is readable/writable while the USB module stop 2 bit (MSTPB0) in MSTPCRB is 1.
When an interrupt flag is set while the corresponding bit in UIER3 is set to 1, an interrupt is
requested by asserting the corresponding EXIRQ0 or EXIRQ1. Either EXIRQ0 or EXIRQ1 must
be selected by the interrupt select register 3 (UISR3). Note, however, that the SPRSiE bit is an
interrupt enable bit specific to the IRQ6 pin and cannot be selected by UISR3.
Bit
7 to 4 —
3
2
1
0
Bit
7
6
5
4, 3
2
1
0
Bit Name
—
EP2READYE 0
EP1TRE
EP1EMPTYE 0
Bit Name
CK48READYE 1
SOFE
SETCE
—
SPRSiE
—
VBUSiE
All 0
0
0
Initial Value R/W
Initial Value
0
0
All 0
0
0
0
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R
R/W
Description
Reserved
These bits are always read as 0.
Reserved
The write value should always be 0.
Enables the EP2READY interrupt.
Enables the EP1TR interrupt.
Enables the EP1EMPTYE interrupt.
Description
Enables the CK48READY interrupt.
Enables the SOF interrupt.
Enables the SETC interrupt.
Reserved
These bits are always read as 0.
Enables the SPRSi interrupt. (only for IRQ6)
Reserved
This bit is always read as 0.
Enables the VBUSi interrupt.
Rev.7.00 Dec. 24, 2008 Page 485 of 698
REJ09B0074-0700