DF2218BR24V Renesas Electronics America, DF2218BR24V Datasheet - Page 184
![IC H8S/2218 MCU FLASH 112-LFBGA](/photos/12/42/124228/df2218br24v_sml.jpg)
DF2218BR24V
Manufacturer Part Number
DF2218BR24V
Description
IC H8S/2218 MCU FLASH 112-LFBGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Specifications of DF2218BR24V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
24MHz
Connectivity
SCI, SmartCard, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
112-LFBGA
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW3DK2218 - DEV EVAL KIT H8S/2218
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2218BR24V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 184 of 758
- Download datasheet (5Mb)
Section 6 Bus Controller
6.4.2
Bus Specifications
The external space bus specifications consist of three elements: bus width, number of access states,
and number of program wait states.
The bus width and number of access states for memory and internal I/O registers except for the on-
chip USB and RTC are fixed, and are not affected by the bus controller.
Bus Width: A bus width of 8 or 16 bits can be selected with ABWCR. An area for which an 8-bit
bus is selected functions as an 8-bit access space, and an area for which a 16-bit bus is selected
functions as a16-bit access space.
If all areas are designated for 8-bit access, 8-bit bus mode is set; if any area is designated for 16-bit
access, 16-bit bus mode is set. When the burst ROM interface is designated, 16-bit bus mode is
always set. 8-bit bus mode should be set for area 6 and area 7 in this LSI.
Number of Access States: Two or three access states can be selected with ASTCR.
An area for which 2-state access is selected functions as a 2-state access space, and an area for
which 3-state access is selected functions as a 3-state access space.
With the burst ROM interface, the number of access states may be determined without regard to
ASTCR.
When 2-state access space is designated, wait insertion is disabled.
Area 6 and area 7 should be set to function as a 3-state access space in this LSI.
Number of Program Wait States: When 3-state access space is designated by ASTCR, the
number of program wait states to be inserted automatically is selected with WCRH and WCRL.
From 0 to 3 program wait states can be selected.
The number of program wait states in area 6 and area 7 should be set to 0 in this LSI.
Rev.7.00 Dec. 24, 2008 Page 128 of 698
REJ09B0074-0700
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