DF2218BR24V Renesas Electronics America, DF2218BR24V Datasheet - Page 681

IC H8S/2218 MCU FLASH 112-LFBGA

DF2218BR24V

Manufacturer Part Number
DF2218BR24V
Description
IC H8S/2218 MCU FLASH 112-LFBGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheets

Specifications of DF2218BR24V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
24MHz
Connectivity
SCI, SmartCard, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
112-LFBGA
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW3DK2218 - DEV EVAL KIT H8S/2218
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2218BR24V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
20.8
20.8.1
When the SLEEP instruction is executed with the SBYCR SSBY bit = 0, LPWRCR LSON bit = 1,
and TCSR_1 PSS bit = 1, CPU operation shifts to subsleep mode.
In subsleep mode, the CPU is stopped. Peripheral modules other WDT and RTC are also stopped.
The contents of the CPU's internal registers, the data in internal RAM, and the statuses of the
internal peripheral modules (excluding the A/D converter) and I/O ports are retained.
20.8.2
Subsleep mode is exited by an interrupt (interrupts from internal peripheral modules, NMI pin, or
IRQ0, to IRQ7), or signals at the RES, MRES*, or STBY pin.
• Exiting Subsleep Mode by Interrupts
• Exiting Subsleep Mode by RES or MRES* pin
• Exiting Subsleep Mode by STBY Pin
Note: * Supported only by the H8S/2218 Group.
When an interrupt occurs, subsleep mode is exited and interrupt exception processing starts.
In case of IRQ0, to IRQ7interrupts, subsleep mode is not cancelled if the corresponding enable
bit/pin function switching bit has been cleared to 0, and, in the case of interrupts from the
internal peripheral modules, the interrupt enable register has been set to disable the reception of
that interrupt, or is masked by the CPU.
For exiting subsleep mode by the RES or MRES* pin, see section 20.4.2, Clearing Software
Standby Mode.
When the STBY pin level is driven low, a transition is made to hardware standby mode.
Subsleep Mode
Transition to Sleep Mode
Exiting Subsleep Mode
Rev.7.00 Dec. 24, 2008 Page 625 of 698
REJ09B0074-0700

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