DF2218BR24V Renesas Electronics America, DF2218BR24V Datasheet - Page 350

• Manufacturer Part Number: DF2218BR24V
• Description: IC H8S/2218 MCU FLASH 112-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2218BR24V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: SCI, SmartCard, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-LFBGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW3DK2218 - DEV EVAL KIT H8S/2218
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

9.3.5
The TSR registers indicate the status of each channel. The TPU has three TSR registers, one for
each channel.
Rev.7.00 Dec. 24, 2008 Page 294 of 698
REJ09B0074-0700
Bit
1
0
Bit
7
6
5
Bit Name Initial value
TGIEB
TGIEA
Bit Name Initial value
TCFD
–
TCFU
Timer Status Register (TSR)
0
0
1
1
0
R/W
R
–
R/(W)* Underflow Flag
R/W
R/W
R/W
Description
TGR Interrupt Enable B
Enables or disables interrupt requests (TGIB) by the
TGFB bit when the TGFB bit in TSR is set to 1.
0: Interrupt requests (TGIB) by TGFB disabled
1: Interrupt requests (TGIB) by TGFB enabled
TGR Interrupt Enable A
Enables or disables interrupt requests (TGIA) by the
TGFA bit when the TGFA bit in TSR is set to 1.
0: Interrupt requests (TGIA) by TGFA disabled
1: Interrupt requests (TGIA) by TGFA enabled
Description
Count Direction Flag
Status flag that shows the direction in which TCNT counts
in channel 1 and 2. In channel 0, bit 7 is reserved. It is
always read as 0 and cannot be modified.
0: TCNT counts down
1: TCNT counts up
Reserved
This bit is always read as 1 and cannot be modified.
Status flag that indicates that TCNT underflow has
occurred when channels 1 and 2 are set to phase
counting mode. The write value should always be 0 to
clear this flag. In channel 0, bit 5 is reserved.
[Setting condition]
[Clearing condition]
When the TCNT value underflows (change from H'0000
to H'FFFF)
When 0 is written to TCFU after reading TCFU = 1