DF2218BR24V Renesas Electronics America, DF2218BR24V Datasheet - Page 396

IC H8S/2218 MCU FLASH 112-LFBGA

DF2218BR24V

Manufacturer Part Number
DF2218BR24V
Description
IC H8S/2218 MCU FLASH 112-LFBGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheets

Specifications of DF2218BR24V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
24MHz
Connectivity
SCI, SmartCard, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
112-LFBGA
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW3DK2218 - DEV EVAL KIT H8S/2218
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2218BR24V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
10.2
The WDT has the following three registers. For details, refer to section 21, List of Registers. To
prevent accidental overwriting, TCSR, TCNT, and RSTCSR have to be written to by a different
method to normal registers. For details, refer to section 10.5.1, Notes on Register Access.
• Timer counter (TCNT)
• Timer control/status register (TCSR)
• Reset control/status register (RSTCSR)
10.2.1
TCNT is an 8-bit readable/writable up-counter. TCNT is initialized to H'00 by a reset, when the
TME bit in TCSR is cleared to 0.
10.2.2
TCSR is an 8-bit readable/writable register. Its functions include selecting the clock source to be
input to TCNT, and selecting the timer mode.
Rev.7.00 Dec. 24, 2008 Page 340 of 698
REJ09B0074-0700
Register Descriptions
Timer Counter (TCNT)
Timer Control/Status Register (TCSR)
Internal reset signal*
(interrupt request
Legend:
TCSR:
TCNT:
RSTCSR:
Notes: When a sub-block is operating, φ will be φ
* The type of internal reset signal depends on a register setting.
signal)
WOVI
Timer control/status register
Timer counter
Reset control/status register
Figure 10.1 Block Diagram of WDT
RSTCSR
Interrupt
control
control
Reset
Overflow
Module bus
TCNT
Clock
SUB
WDT
.
Clock
select
TSCR
Internal clock
sources
interface
Bus
φ/2
φ/64
φ/128
φ/512
φ/2048
φ/8192
φ/32768
φ/131072

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