DF2218BR24V Renesas Electronics America, DF2218BR24V Datasheet - Page 425

• Manufacturer Part Number: DF2218BR24V
• Description: IC H8S/2218 MCU FLASH 112-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2218BR24V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: SCI, SmartCard, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-LFBGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW3DK2218 - DEV EVAL KIT H8S/2218
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.3.5
SMR is used to set the SCI's serial transfer format and select the baud rate generator clock source.
Some bits in SMR have different functions in normal mode and smart card interface mode.
• Normal Serial Communication Interface Mode (When SMIF in SCMR is 0)
Bit
7
6
5
4
3
Bit Name Initial Value
C/A
CHR
PE
O/E
STOP
Serial Mode Register (SMR)
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
0: Asynchronous mode
1: Clocked synchronous mode
0: 1 stop bit
1: 2 stop bits
Description
Communication Mode
Character Length (enabled only in asynchronous mode)
0: Selects 8 bits as the data length
1: Selects 7 bits as the data length. LSB-first is fixed
In clocked synchronous mode, a fixed data length of 8
bits is used.
Parity Enable (enabled only in asynchronous mode)
When this bit is set to 1, the parity bit is added to
transmit data before transmission, and the parity bit is
checked in reception. For a multiprocessor format, parity
bit addition and checking are not performed regardless
of the PE bit setting.
Parity Mode (enabled only when the PE bit is 1 in
asynchronous mode)
Stop Bit Length (enabled only in asynchronous mode)
Selects the stop bit length in transmission.
In reception, only the first stop bit is checked. If the
second stop bit is 0, it is treated as the start bit of the
next transmit character.
0: Selects even parity
1: Selects odd parity
and the MSB of TDR is not transmitted in
transmission
Rev.7.00 Dec. 24, 2008 Page 369 of 698
REJ09B0074-0700