DF2218BR24V Renesas Electronics America, DF2218BR24V Datasheet - Page 529

IC H8S/2218 MCU FLASH 112-LFBGA

DF2218BR24V

Manufacturer Part Number
DF2218BR24V
Description
IC H8S/2218 MCU FLASH 112-LFBGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheets

Specifications of DF2218BR24V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
24MHz
Connectivity
SCI, SmartCard, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
112-LFBGA
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW3DK2218 - DEV EVAL KIT H8S/2218
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2218BR24V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
14.3.4
UTRG0 is a one-shot register to generate triggers to the FIFO for each endpoint EP0 to EP3. For
details, see section 2.9.4, Accessing Registers Containing Write-Only Bits.
Bit
7, 6
5
4
3
2
1
Bit Name
EP2RDFN
EP1PKTE
EP3PKTE
EP0oRDFN 0
EP0iPKTE
USB Trigger Register 0 (UTRG0)
Initial Value R/W
All 0
0
0
0
0
R
W
W
W
W
W
Description
Reserved
These bits are always read as 0 and cannot be
modified.
EP2 Read Complete
0: Performs no operation.
1: Writes 1 to this bit after reading data for EP2 OUT
EP1 Packet Enable
0: Performs no operation.
1: Generates a trigger to enable the transmission to
EP3 Packet Enable
0: Performs no operation.
1: Generates a trigger to enable the transmission to
EP0o Read Complete
0: Performs no operation.
1: Writes 1 to this bit after reading data for EP0o OUT
EP0i Packet Enable
0: Performs no operation.
1: Generates a trigger to enable the transmission to
FIFO. EP2 has a dual-FIFO configuration. This
trigger is generated to the currently effective FIFO.
EP1 IN FIFO. EP1 has a dual-FIFO configuration.
This trigger is generated to the currently effective
FIFO.
EP3 IN FIFO.
FIFO. This trigger enables EP0o to receive the
next packet.
EP0i IN FIFO.
Rev.7.00 Dec. 24, 2008 Page 473 of 698
REJ09B0074-0700

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