DF2218BR24V Renesas Electronics America, DF2218BR24V Datasheet - Page 232

• Manufacturer Part Number: DF2218BR24V
• Description: IC H8S/2218 MCU FLASH 112-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2218BR24V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: SCI, SmartCard, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-LFBGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW3DK2218 - DEV EVAL KIT H8S/2218
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Rev.7.00 Dec. 24, 2008 Page 176 of 698
REJ09B0074-0700
Bit Bit Name Initial Value R/W
3
2
1
0
DTIE1B
DTIE1A
DTIE0B
DTIE0A
0
0
0
0
R/W
R/W
R/W
R/W
Description
Data Transfer Interrupt Enable B
Enables or disables an interrupt to the CPU when transfer is
interrupted. If the DTIEB bit is set to 1 when DTME = 0, the
DMAC regards this as indicating a break in the transfer, and
issues a transfer break interrupt request to the CPU. A
transfer break interrupt can be canceled either by clearing the
DTIEB bit to 0 in the interrupt handling routine, or by
performing processing to continue transfer by setting the
DTME bit to 1.
Data Transfer Interrupt Enable 1B
Enables or disables the channel 1 transfer break interrupt.
0: Transfer break interrupt disabled
1: Transfer break interrupt enabled
Data Transfer End Interrupt Enable A
Enables or disables an interrupt to the CPU when transfer
ends. If the DTIEA bit is set to 1 when DTE = 0, the DMAC
regards this as indicating the end of a transfer, and issues a
transfer end interrupt request to the CPU. A transfer end
interrupt can be canceled either by clearing the DTIEA bit to 0
in the interrupt handling routine, or by performing processing
to continue transfer by setting the DTE bit to 1.
Data Transfer End Interrupt Enable 1A
Enables or disables the channel 1 transfer end interrupt.
0: Transfer end interrupt disabled
1: Transfer end interrupt enabled
Data Transfer Interrupt Enable 0B
Enables or disables the channel 0 transfer break interrupt.
0: Transfer break interrupt disabled
1: Transfer break interrupt enabled
Data Transfer End Interrupt Enable 0A
Enables or disables the channel 0 transfer end interrupt.
0: Transfer end interrupt disabled
1: Transfer end interrupt enabled