DF2218BR24V Renesas Electronics America, DF2218BR24V Datasheet - Page 674

• Manufacturer Part Number: DF2218BR24V
• Description: IC H8S/2218 MCU FLASH 112-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2218BR24V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: SCI, SmartCard, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-LFBGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW3DK2218 - DEV EVAL KIT H8S/2218
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Figure 20.3 shows the timing for transition to and clearance of medium-speed mode.
Note: * Supported only by the H8S/2218 Group.
20.3
20.3.1
When the SLEEP instruction is executed when the SSBY bit in SBYCR and the LSON bit in
LPWRCR are cleared to 0, the CPU enters the sleep mode. In sleep mode, CPU operation stops
but the contents of the CPU's internal registers are retained. Other supporting modules do not stop.
20.3.2
Sleep mode is exited by any interrupt, or signals at the RES, MRES*, or STBY pin.
• Exiting Sleep Mode by Interrupts
• Exiting Sleep Mode by RES or MRES* Pin
• Exiting Sleep Mode by STBY Pin
Note: * Supported only by the H8S/2218 Group.
Rev.7.00 Dec. 24, 2008 Page 618 of 698
REJ09B0074-0700
When an interrupt occurs, sleep mode is exited and interrupt exception processing starts. Sleep
mode is not exited if the interrupt is disabled, or interrupts other than NMI are masked by the
CPU.
Setting the RES or MRES* pin level Low selects the reset state. After the stipulated reset input
duration, driving the RES or MRES* pin High starts the CPU performing reset exception
processing.
When the STBY pin level is driven Low, a transition is made to hardware standby mode.
φ,
supporting module clock
Bus master clock
Internal address bus
Internal write signal
Sleep Mode
Transition to Sleep Mode
Exiting Sleep Mode
Figure 20.3 Medium-Speed Mode Transition and Clearance Timing
SCKCR
Medium-speed mode
SCKCR