DF2218BR24V Renesas Electronics America, DF2218BR24V Datasheet - Page 493

• Manufacturer Part Number: DF2218BR24V
• Description: IC H8S/2218 MCU FLASH 112-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2218BR24V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: SCI, SmartCard, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-LFBGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW3DK2218 - DEV EVAL KIT H8S/2218
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

When turning on the power or switching between Smart Card interface mode and software standby
mode, the following procedures should be followed in order to maintain the clock duty.
Powering On: To secure clock duty from power-on, the following switching procedure should be
followed.
When changing from smart card interface mode to software standby mode:
When returning to smart card interface mode from software standby mode:
1. The initial state is port input and high impedance. Use a pull-up resistor or pull-down
2. Fix the SCK pin to the specified output level with the CKE1 bit in SCR.
3. Set SMR and SCMR, and switch to smart card mode operation.
4. Set the CKE0 bit in SCR to 1 to start clock output.
1. Set the data register (DR) and data direction register (DDR) corresponding to the SCK pin
2. Write 0 to the TE bit and RE bit in the serial control register (SCR) to halt transmit/receive
3. Write 0 to the CKE0 bit in SCR to halt the clock.
4. Wait for one serial clock period.
5. Make the transition to the software standby state.
1. Exit the software standby state.
2. Write 1 to the CKE0 bit in SCR and output the clock. Signal generation is started with the
resistor to fix the potential.
to the value for the fixed output state in software standby mode.
operation. At the same time, set the CKE1 bit to the value for the fixed output state in
software standby mode.
During this interval, clock output is fixed at the specified level, with the duty preserved.
normal duty.
Figure 12.35 Clock Halt and Restart Procedure
Normal operation
Software
standby
Rev.7.00 Dec. 24, 2008 Page 437 of 698
Normal operation
REJ09B0074-0700