DF2218BR24V Renesas Electronics America, DF2218BR24V Datasheet - Page 488

• Manufacturer Part Number: DF2218BR24V
• Description: IC H8S/2218 MCU FLASH 112-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2218BR24V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: SCI, SmartCard, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-LFBGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW3DK2218 - DEV EVAL KIT H8S/2218
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.7.7
As data transmission in Smart Card interface mode involves error signal sampling and
retransmission processing, the operations are different from those in normal serial communication
interface mode (except for block transfer mode). Figure 12.29 illustrates the retransfer operation
when the SCI is in transmit mode.
1. If an error signal is sent back from the receiving end after transmission of one frame is
2. The TEND bit in SSR is not set for a frame in which an error signal indicating an abnormality
3. If an error signal is not sent back from the receiving end, the ERS bit in SSR is not set.
Figure 12.31 shows a flowchart for transmission. A sequence of transmit operations can be
performed automatically by specifying the DMAC to be activated with a TXI interrupt source. In a
transmit operation, the TDRE flag is set to 1 at the same time as the TEND flag in SSR is set, and
a TXI interrupt will be generated if the TIE bit in SCR has been set to 1. If the TXI request is
designated beforehand as a DMAC activation source, the DMAC will be activated by the TXI
request, and transfer of the transmit data will be carried out. The TDRE and TEND flags are
automatically cleared to 0 when data is transferred by the DMAC. In the event of an error, the SCI
retransmits the same data automatically. During this period, the TEND flag remains cleared to 0
and the DMAC is not activated. Therefore, the SCI and DMAC will automatically transmit the
specified number of bytes in the event of an error, including retransmission. However, the ERS
flag is not cleared automatically when an error occurs, and so the RIE bit should be set to 1
beforehand so that an ERI request will be generated in the event of an error, and the ERS flag will
be cleared. When using the DMAC for data transmission or reception, always make DMAC
settings and enable the DMAC before making SCI settings. For details on DMAC settings, see
section 7, DMA Controller (DMAC).
Rev.7.00 Dec. 24, 2008 Page 432 of 698
REJ09B0074-0700
complete, the ERS bit in SSR is set to 1. If the RIE bit in SCR is enabled at this time, an ERI
interrupt request is generated. The ERS bit in SSR should be cleared to 0 by the time the next
parity bit is sampled.
is received. Data is retransferred from TDR to TSR, and retransmitted automatically.
Transmission of one frame, including a retransfer, is judged to have been completed, and the
TEND bit in SSR is set to 1. If the TIE bit in SCR is enabled at this time, a TXI interrupt
request is generated. Writing transmit data to TDR transfers the next transmit data.
Serial Data Transmission (Except for Block Transfer Mode)