DF2218BR24V Renesas Electronics America, DF2218BR24V Datasheet - Page 451

• Manufacturer Part Number: DF2218BR24V
• Description: IC H8S/2218 MCU FLASH 112-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2218BR24V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: SCI, SmartCard, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-LFBGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW3DK2218 - DEV EVAL KIT H8S/2218
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.3.11 Bit Rate Register (BRR)
BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control
independently for each channel, different bit rates can be set for each channel. Table 12.2 shows
the relationships between the N setting in BRR and bit rate B for normal asynchronous mode,
clocked synchronous mode, and Smart Card interface mode. The initial value of BRR is H'FF, and
it can be read from or written to by the CPU at all times.
Table 12.2 Relationships between the N Setting in BRR and Bit Rate B
Legend:
B:
N:
φ:
n, S: Determined by the SMR settings shown in the following tables.
×:
Table 12.3 shows sample N settings in BRR in normal asynchronous mode. Table 12.4 shows the
maximum bit rate for each frequency in normal asynchronous mode. Table 12.6 shows sample N
settings in BRR in clocked synchronous mode. Table 12.8 shows sample N settings in BRR in
Smart Card interface mode. In Smart Card interface mode, S (the number of basic clock periods in
a 1-bit transfer interval) can be selected. For details, see section 12.7.5, Receive Data Sampling
Mode
Asynchronous
mode
Clocked
synchronous
mode
Smart Card
interface mode
CKS1
0
0
1
1
Bit rate (bps)
BRR setting for baud rate generator (0 ≤ N ≤ 255)
Operating frequency (MHz)
Don’t care
SMR Setting
CKS0
0
1
0
1
ABCS
0
1
×
×
Clock Source
φ
φ/4
φ/16
φ/64
Bit Rate
B =
B =
B =
B =
64 × 2
32 × 2
8 × 2
S × 2
φ × 10
2n-1
2n+1
φ × 10
φ × 10
2n-1
2n-1
φ × 10
× (N + 1)
× (N + 1)
× (N + 1)
× (N + 1)
6
n
0
1
2
3
6
6
6
Error
Error (%) =
Error (%) =
⎯
Error (%) =
Rev.7.00 Dec. 24, 2008 Page 395 of 698
BCP1
0
0
1
1
SMR Setting
B × 64 × 2
B × 32 × 2
B × S × 2
BCP0
0
1
0
1
φ × 10
φ × 10
φ × 10
2n+1
2n-1
2n-1
× (N + 1)
× (N + 1)
× (N + 1)
6
6
6
REJ09B0074-0700
S
32
64
372
256
– 1 × 100
– 1 × 100
– 1 × 100