DF2218BR24V Renesas Electronics America, DF2218BR24V Datasheet - Page 295

• Manufacturer Part Number: DF2218BR24V
• Description: IC H8S/2218 MCU FLASH 112-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2218BR24V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: SCI, SmartCard, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-LFBGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW3DK2218 - DEV EVAL KIT H8S/2218
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

8.7
The port B is an 8-bit I/O port also functioning as address bus (A15 to A8) output pins. The port B
has the following registers.
Note: When the USB is used while the E6000 emulator is used, the AE3 to AE0 bits in PFCR
• Port B data direction register (PBDDR)
• Port B data register (PBDR)
• Port B register (PORTB)
• Port B pull-up MOS control register (PBPCR)
8.7.1
PBDDR specifies input or output for the pins of the port B.
Since PBDDR is a write-only register, the bit manipulation instructions must not be used to write
PBDDR. For details, see section 2.9.4, Accessing Registers Containing Write-Only Bits.
Bit
7
6
5
4
3
2
1
0
Bit Name Initial Value
PB7DDR
PB6DDR
PB5DDR
PB4DDR
PB3DDR
PB2DDR
PB1DDR
PB0DDR
must be set so that the PB1 and PB0 pins output addresses A9 and A8. This note applies to
both the H8S/2218 Group and H8S/2212 Group.
Port B (H8S/2218 Group Only)
Port B Data Direction Register (PBDDR)
0
0
0
0
0
0
0
0
R/W
W
W
W
W
W
W
W
W
Modes 4 to 6:
If address output is enabled by the setting of bits AE3 to
AE0 in PFCR, the corresponding port B pins are address
outputs. When address output is disabled, setting a
PBDDR bit to 1 makes the corresponding port B pin an
output port, while clearing the bit to 0 makes the pin an
input port.
Mode 7:
Setting a PBDDR bit to 1 makes the corresponding port B
pin an output port, while clearing the bit to 0 makes the
pin an input port.
Description
Rev.7.00 Dec. 24, 2008 Page 239 of 698
REJ09B0074-0700