DF2218BR24V Renesas Electronics America, DF2218BR24V Datasheet - Page 600

IC H8S/2218 MCU FLASH 112-LFBGA

DF2218BR24V

Manufacturer Part Number
DF2218BR24V
Description
IC H8S/2218 MCU FLASH 112-LFBGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheets

Specifications of DF2218BR24V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
24MHz
Connectivity
SCI, SmartCard, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
112-LFBGA
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW3DK2218 - DEV EVAL KIT H8S/2218
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2218BR24V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
15.5.3
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input when the A/D conversion start delay time (t
starts conversion. Figure 15.5 shows the A/D conversion timing. Tables 15.3 and 15.4 show the
A/D conversion time.
As indicated in figure 15.5, the A/D conversion time (t
time (t
total conversion time therefore varies within the ranges indicated in table 15.4.
In scan mode, the values given in table 15.4 apply to the first conversion time. The values given in
table 15.3 apply to the second and subsequent conversions.
Rev.7.00 Dec. 24, 2008 Page 544 of 698
REJ09B0074-0700
SPL
). The length of t
Input Sampling and A/D Conversion Time
Address
Write signal
Input sampling
timing
ADF
φ
Legend:
(1):
(2):
t
t
t
D
SPL
CONV
:
:
: A/D conversion time
ADCSR write cycle
ADCSR address
A/D conversion start delay
Input sampling time
D
varies depending on the timing of the write access to ADCSR. The
Figure 15.5 A/D Conversion Timing
(1)
(2)
t
D
t
SPL
D
) has passed after the ADST bit is set to 1, then
t
CONV
CONV
) includes t
D
and the input sampling

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