DF2218BR24V Renesas Electronics America, DF2218BR24V Datasheet - Page 526

• Manufacturer Part Number: DF2218BR24V
• Description: IC H8S/2218 MCU FLASH 112-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2218BR24V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: SCI, SmartCard, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-LFBGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW3DK2218 - DEV EVAL KIT H8S/2218
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Rev.7.00 Dec. 24, 2008 Page 470 of 698
REJ09B0074-0700
Bit
1
0
Bit Name
UIFRST
UDCRST
Initial Value R/W
1
1
R/W
R/W
Description
USB Interface Software Reset
Controls USB module internal reset. When the
UIFRST bit is set to 1, the USB internal modules other
than UCTLR, UIER3, and the CK48READY bit in
UIFR3 are all reset. At initialization, the UIFRST bit
must be cleared to 0 after the USB operating clock (48
MHz) stabilization time has passed following the
clearing of the USB module stop 2 bit.
0: Sets the USB internal modules to the operating
1: Sets the USB internal modules other than UCTLR,
If the UIFRST bit is set to 1 after it is cleared to 0, the
UDCRST bit should also be set to 1 simultaneously.
UDC Core Software Reset
Controls reset of the UDC core in the USB module.
When the UDCRST bit is set to 1, the UDC core is
reset and the USB bus synchronization operation
stops. At initialization, UDCRST must be cleared to 0
after D+ pull-up by the port (P36) control following the
clearing of the UIFRST bit. In the suspend state, to
maintain the internal state of the UDC core, enter
power-down mode after setting the USB module stop
2 bit with the UDCRST bit to be maintained to 0. After
VBUS disconnection detection, UDCRST must be set
to 1.
0: Sets the UDC core in the USB module to operating
1: Sets the UDC core in the USB module to reset
state. (At initialization, this bit must be cleared after
the USB operating clock stabilization time has
passed.)
UIER3, and the CK48READY bit in UIFR3 to the
reset state.
state. (At initialization, UDCRST must be cleared
to 0 after D+ pull-up by the port control following
the clearing of the UIFRST bit.)
state. (In the suspend state, UDCRST must not be
set to 1; after VBUS disconnection detection,
UDCRST must be set to 1.)