DF2218BR24V Renesas Electronics America, DF2218BR24V Datasheet - Page 335

• Manufacturer Part Number: DF2218BR24V
• Description: IC H8S/2218 MCU FLASH 112-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2218BR24V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: SCI, SmartCard, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-LFBGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW3DK2218 - DEV EVAL KIT H8S/2218
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

9.3.1
The TCR registers control the TCNT operation for each channel. The TPU has a total of three TCR
registers, one for each channel (channel 0 to 2). TCR register settings should be made only when
TCNT operation is stopped.
Bit
7
6
5
4
3
2
1
0
Bit Name Initial value
CCLR2
CCLR1
CCLR0
CKEG1
CKEG0
TPSC2
TPSC1
TPSC0
Timer Control Register (TCR)
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Counter Clear 2 to 0
These bits select the TCNTcounter clearing source. See
tables 9.3 and 9.4 for details.
Clock Edge 1 and 0
These bits select the input clock edge. When the internal
clock is counted using both edges, the input clock
frequency is halved (e.g., φ/4 both edges = φ/2 rising
edge). If phase counting mode is used on channels 1, 2,
4, and 5, this setting is ignored and the phase counting
mode setting has priority. Internal clock edge selection is
valid when the input clock is φ/4 or slower. If φ/1 is
selected as the input clock, this setting is ignored and
count at falling edge of φ is selected.
00: Count at rising edge
01: Count at falling edge
1×: Count at both edges
Legend:
×: Don’t care
Time Prescaler 2 to 0
These bits select the TCNT counter clock. The clock
source can be selected independently for each channel.
See tables 9.5 to 9.7 for details.
Description
Rev.7.00 Dec. 24, 2008 Page 279 of 698
REJ09B0074-0700