DF2218BR24V Renesas Electronics America, DF2218BR24V Datasheet - Page 154

• Manufacturer Part Number: DF2218BR24V
• Description: IC H8S/2218 MCU FLASH 112-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2218BR24V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: SCI, SmartCard, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-LFBGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW3DK2218 - DEV EVAL KIT H8S/2218
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Legend:
×: Don’t care
Notes: 1. IRQ6 is an interrupt only for the on-chip USB.
5.3.4
ISR indicates the status of IRQ7 to IRQ0 interrupt requests.
Note: * Only 0 can be written, to clear flags.
Rev.7.00 Dec. 24, 2008 Page 98 of 698
REJ09B0074-0700
Bit
1
0
Bit
7
6
5
4
3
2
1
0
Bit Name
IRQ7F
IRQ6F
IRQ5F
IRQ4F
IRQ3F
IRQ2F
IRQ1F
IRQ0F
2. IRQ5 is an interrupt only for the on-chip RTC.
Bit Name
IRQ0SCB
IRQ0SCA
IRQ Status Register (ISR)
Initial Value R/W
0
0
0
0
0
0
0
0
Initial Value R/W
0
0
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/W
R/W
Description
[Setting condition]
When the interrupt source selected by the ISCR
registers occurs
[Clearing conditions]
•
•
•
Description
IRQ0 Sense Control B
IRQ0 Sense Control A
00: Interrupt request generated at IRQ0 input low level
01: Interrupt request generated at falling edge of IRQ0
10: Interrupt request generated at rising edge of IRQ0
11: Interrupt request generated at both falling and
Cleared by reading IRQnF flag when IRQnF = 1,
then writing 0 to IRQnF flag
When interrupt exception handling is executed
when low-level detection is set and , IRQn input is
high
When IRQn interrupt exception handling is executed
when falling, rising, or both-edge detection is set
input
input
rising edges of IRQ0 input