DF2218BR24V Renesas Electronics America, DF2218BR24V Datasheet - Page 156

• Manufacturer Part Number: DF2218BR24V
• Description: IC H8S/2218 MCU FLASH 112-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2218BR24V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: SCI, SmartCard, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-LFBGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW3DK2218 - DEV EVAL KIT H8S/2218
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

The set timing for IRQnF is shown in figure 5.3.
The detection of IRQn interrupts does not depend on whether the relevant pin has been set for
input or output. However, when a pin is used as an external interrupt input pin, do not clear the
corresponding DDR to 0; and use the pin as an I/O pin for another function. IRQnF interrupt
request flag is set when the setting condition is satisfied, regardless of IER settings. Accordingly,
refer to only necessary flags.
5.4.2
The sources for internal interrupts from on—chip peripheral modules have the following features:
• For each on—chip peripheral module there are flags that indicate the interrupt request status,
• The interrupt priority level can be set by means of IPR.
• The DMAC can be activated by a TPU, SCI, or other interrupt request.
• When the DMAC is activated by an interrupt request, it is not affected by the interrupt control
Rev.7.00 Dec. 24, 2008 Page 100 of 698
REJ09B0074-0700
and enable bits that select enabling or disabling of these interrupts. If both of these are set to 1
for a particular interrupt source, an interrupt request is issued to the interrupt controller.
mode or CPU interrupt mask bit.
IRQn
input pin
IRQnF
Internal Interrupts
Note: n = 7 to 0
Figure 5.3 Timing of Setting IRQnF