DF2218BR24V Renesas Electronics America, DF2218BR24V Datasheet - Page 625
![IC H8S/2218 MCU FLASH 112-LFBGA](/photos/12/42/124228/df2218br24v_sml.jpg)
DF2218BR24V
Manufacturer Part Number
DF2218BR24V
Description
IC H8S/2218 MCU FLASH 112-LFBGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Specifications of DF2218BR24V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
24MHz
Connectivity
SCI, SmartCard, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
112-LFBGA
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW3DK2218 - DEV EVAL KIT H8S/2218
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2218BR24V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 625 of 758
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5. In boot mode, a part of the on-chip RAM area (four kbytes) is used by the boot program. The
6. Before branching to the programming control program, the chip terminates transfer operations
7. Boot mode can be cleared by a reset. End the reset* after driving the reset pin low, waiting at
8. Do not change the MD pin input levels in boot mode. If the mode pin input levels are changed
9. All interrupts are disabled during programming or erasing of the flash memory.
Note:* Mode pin and FWE pin input must satisfy the mode programming setup time (t
area to which the programming control program is transferred from the host is 8 kbytes
(H'FFC000 to H'FFDFFF) in the HD64F2218 and HD64F2212 and 4 kbytes (H'FFD000 to
H'FFDFFF) in the HD64F2211. The boot program area cannot be used until the execution
state in boot mode switches to the programming control program.
by the SCI_2 (by clearing the RE and TE bits in SCR to 0), but the adjusted bit rate value
remains set in BRR. Therefore, the programming control program can still use it for transfer of
write data or verify data with the host. The TxD pin is high. The contents of the CPU general
registers are undefined immediately after branching to the programming control program.
These registers must be initialized at the beginning of the programming control program, since
the stack pointer (SP), in particular, is used implicitly in subroutine calls, etc.
least 20 states, and then setting the FWE pin and the mode (MD) pins. Boot mode is also
cleared when a WDT overflow occurs.
(for example, from low to high) during a reset, the state of ports with multiplexed address
functions and bus control output pins (AS, RD, WR) will change according to the change in
the microcomputer’s operating mode . Therefore, care must be taken to make pin settings to
prevent these pins from becoming output signal pins during a reset, or to prevent collision with
signals outside the microcomputer.
ns) with respect to the reset release timing.
Rev.7.00 Dec. 24, 2008 Page 569 of 698
REJ09B0074-0700
MDS
= 200
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