DF2218BR24V Renesas Electronics America, DF2218BR24V Datasheet - Page 250

• Manufacturer Part Number: DF2218BR24V
• Description: IC H8S/2218 MCU FLASH 112-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2218BR24V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: SCI, SmartCard, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-LFBGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW3DK2218 - DEV EVAL KIT H8S/2218
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

7.4.7
DMAC activation sources consist of internal interrupts, external requests, and auto-requests. The
activation sources that can be specified depend on the transfer mode, as shown in table 7.8.
Table 7.8
Activation
Source
Internal
Interrupt
USB request Low level input of the DREQ
Auto-request
Legend:
×:
Activation by Internal Interrupt: An interrupt request selected as a DMAC activation source can
be sent simultaneously to the CPU. For details, see section 5, Interrupt Controller.
With activation by an internal interrupt, the DMAC accepts the request independently of the
interrupt controller. Consequently, interrupt controller priority settings are not accepted.
If the DMAC is activated by an interrupt request that is not used as a CPU interrupt source (DTA =
1), the interrupt source flag is cleared automatically by the DMA transfer. With ADI, TXI, and
RXI interrupts, however, the interrupt source flag is not cleared unless the prescribed register is
accessed in a DMA transfer. If the same interrupt is used as an activation source for more than one
channel, the interrupt request flag is cleared when the highest-priority channel is activated first.
Transfer requests for other channels are held pending in the DMAC, and activation is carried out in
order of priority.
When DTE = 0, such as after completion of a transfer, a request from the selected activation
source is not sent to the DMAC, regardless of the DTA bit. In this case, the relevant interrupt
request is sent to the CPU. In case of overlap with a CPU interrupt source (DTA = 0), the interrupt
request flag is not cleared by the DMAC.
Rev.7.00 Dec. 24, 2008 Page 194 of 698
REJ09B0074-0700
: Can be specified
Cannot be specified
DMAC Activation Sources
DMAC Activation Sources
ADI
TXI0
RXI0
TGI0A
TGI1A
TGI2A
signal
Short Address
Mode
×
×
Full Address Mode
Normal Mode
×
×
×
×
×
×
Block Transfer
Mode
×
×