DF2218BR24V Renesas Electronics America, DF2218BR24V Datasheet - Page 48

• Manufacturer Part Number: DF2218BR24V
• Description: IC H8S/2218 MCU FLASH 112-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2218BR24V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: SCI, SmartCard, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-LFBGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW3DK2218 - DEV EVAL KIT H8S/2218
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Figure 22.7 Basic Bus Timing (Two-State Access) ................................................................... 670
Figure 22.8 Basic Bus Timing (Three-State Access) ................................................................. 671
Figure 22.9 Basic Bus Timing (Three-State Access with One Wait State)................................ 672
Figure 22.10 Burst ROM Access Timing (Two-State Access) .................................................... 673
Figure 22.11 External Bus Release Timing ................................................................................. 674
Figure 22.12 I/O Port Input/Output Timing ................................................................................. 677
Figure 22.13 TPU Input/Output Timing ...................................................................................... 677
Figure 22.14 TPU Clock Input Timing ........................................................................................ 677
Figure 22.15 SCK Clock Input Timing........................................................................................ 678
Figure 22.16 SCI Input/Output Timing (Clock Synchronous Mode)........................................... 678
Figure 22.17 A/D Converter External Trigger Input Timing ....................................................... 678
Figure 22.18 Boundary Scan TCK Input Timing......................................................................... 678
Figure 22.19 Boundary Scan TRST Input Timing (At Reset Hold)............................................. 678
Figure 22.20 Boundary Scan Data Transmission Timing ............................................................ 679
Figure 22.21 Data Signal Timing................................................................................................. 681
Figure 22.22 Test Load Circuit .................................................................................................... 681
Appendix
Figure C.1
Figure C.2
Figure C.3
Figure C.4
Rev.7.00 Dec. 24, 2008 Page xlvi of liv
REJ09B0074-0700
TFP-100G and TFP-100GV Package Dimensions ................................................. 691
BP-112 and BP-112V Package Dimensions ........................................................... 692
FP-64E and FP-64EV Package Dimensions ........................................................... 693
TNP-64B and TNP-64BV Package Dimensions .................................................... 694