DF2218BR24V Renesas Electronics America, DF2218BR24V Datasheet - Page 180

• Manufacturer Part Number: DF2218BR24V
• Description: IC H8S/2218 MCU FLASH 112-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2218BR24V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: SCI, SmartCard, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-LFBGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW3DK2218 - DEV EVAL KIT H8S/2218
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.3.4
BCRH selects enabling or disabling of idle cycle insertion, and the memory interface for area 0.
This register should be set initial value and not be modified in the H8S/2212 Group.
Rev.7.00 Dec. 24, 2008 Page 124 of 698
REJ09B0074-0700
Bit
7
6
5
4
3
2 to
0
Bit Name
ICIS1
ICIS0
BRSTRM
BRSTS1
BRSTS0
–
Bus Control Register H (BCRH)
Initial Value R/W
1
1
0
1
0
All 0
R/W
R/W
R/W
R/W
R/W
R/W
Description
Idle Cycle Insert 1:
Selects whether or not one idle cycle state is to be
inserted between bus cycles when successive external
read cycles are performed in different areas.
0: Idle cycle not inserted in case of successive external
1: Idle cycle inserted in case of successive external read
Idle Cycle Insert 0:
Selects whether or not one idle cycle state is to be
inserted between bus cycles when successive external
read and write cycles are performed.
0: Idle cycle not inserted in case of successive external
1: Idle cycle inserted in case of successive external read
Burst ROM enable:
Selects whether area 0 is used as a burst ROM interface.
0: Area 0 is basic bus interface
1: Area 0 is burst ROM interface
Burst Cycle Select 1:
Selects the number of burst cycles for the burst ROM
interface.
0: Burst cycle comprises 1 state
1: Burst cycle comprises 2 states
Burst Cycle Select 0:
Selects the number of words that can be accessed in a
burst ROM interface burst access.
0: Max. 4 words in burst access
1: Max. 8 words in burst access
Reserved
The write value should always be 0.
read cycles in different areas
cycles in different areas
read and write cycles
and write cycles