MC68HC711P2CFN4 Freescale Semiconductor, MC68HC711P2CFN4 Datasheet - Page 120

• Manufacturer Part Number: MC68HC711P2CFN4
• Description: IC MCU 32K OTP 4MHZ 84-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711P2CFN4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Eeprom Size: 640 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Motorola Interconnect Bus (MI BUS)
6.10.4 S2CR2 — MI BUS2 control register 2
6.10.5 S2SR1 — MI BUS2 status register 1
Technical Data
SCI/MI 2 control 2 (S2CR2)
SCI/MI 2 status 1 (S2SR1)
RIE2 — Receiver interrupt enable 2
TE2 — Transmitter enable 2
RE2 — Receiver enable 2
SBK2 — Send break 2
The bits in S2SR1 indicate certain conditions in the MI BUS hardware
and are automatically cleared by special acknowledge sequences. The
receive related flag bits in S2SR1 (RDRF2, OR2 and NF2) are cleared
by a read of this register followed by a read of the transmit/receive data
register. However, only those bits that were set when S2SR1 was read
will be cleared by the subsequent read of the transmit/receive data
Freescale Semiconductor, Inc.
When an MI BUS wire is held low for eight or more time slots an
internal circuit on any slave device connected to the bus may reset or
preset the device with default values.
Address bit 7
Address bit 7
For More Information On This Product,
$0053
$0054 TDRE2 TC2 RDRF2 IDLE2 OR2
1 = MI BUS interrupt requested when RDRF2 flag is set.
0 = RDRF2 and OR2 interrupts disabled.
1 = Transmitter enabled and port pin dedicated to the MI BUS.
0 = Transmitter disabled.
1 = Port pin dedicated to the MI BUS; the receiver is enabled by a
0 = Receiver disabled.
1 = MI transmit line is set low for 20 time slots.
0 = No action.
Motorola Interconnect Bus (MI BUS)
pull sync and is inhibited during a push field.
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TIE2 TCIE2 RIE2
bit 6
bit 6
bit 5
bit 5
ILIE2
bit 4
bit 4
bit 3
bit 3
TE2
RE2 RWU2 SBK2 0000 0000
bit 2
NF2
bit 2
MC68HC11P2 — Rev 1.0
bit 1
FE2
bit 1
bit 0
PF2 1100 0000
bit 0
on reset
on reset
State
State