MC68HC711P2CFN4 Freescale Semiconductor, MC68HC711P2CFN4 Datasheet - Page 181

• Manufacturer Part Number: MC68HC711P2CFN4
• Description: IC MCU 32K OTP 4MHZ 84-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711P2CFN4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Eeprom Size: 640 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

9.5.2 Multiple-channel operation
9.6 Control, status and results registers
9.6.1 ADCTL — A/D control and status register
MC68HC11P2 — Rev 1.0
A/D control & status (ADCTL)
There are two types of multiple-channel operation. In the first type
(SCAN = 0), a selected group of four channels is converted once only.
The first result is stored in A/D result register 1 (ADR1), and the fourth
result is stored in ADR4. After the fourth conversion is complete, all
conversion activity is halted until a new conversion command is written
to the ADCTL register. In the second type of multiple-channel operation
(SCAN = 1), conversions continue to be performed on the selected
group of channels with the fifth conversion being stored in register ADR1
(replacing the earlier conversion result for the first channel in the group),
the sixth conversion overwriting ADR2, and so on.
All bits in this register can be read or written, except bit 7, which is a read-
only status indicator, and bit 6, which always reads as zero. Write to
ADCTL to initiate a conversion. To quit a conversion in progress, write to
this register and a new conversion sequence begins immediately.
CCF — Conversions complete flag
Bit 6 — Not implemented; always reads zero.
Freescale Semiconductor, Inc.
A read-only status indicator, this bit is set when all four A/D result
registers contain valid conversion results. Each time the ADCTL
register is overwritten, this bit is automatically cleared to zero and a
conversion sequence is started. In the continuous mode, CCF is set
at the end of the first conversion sequence.
Address bit 7
For More Information On This Product,
$0030
1 = All four A/D result registers contain valid conversion data.
0 = At least one of the A/D result registers contains invalid data.
Analog-to-Digital Converter
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CCF
bit 6
0
SCAN MULT
bit 5
bit 4
bit 3
CD
Control, status and results registers
bit 2
CC
Analog-to-Digital Converter
bit 1
CB
bit 0
CA
Technical Data
u0uu uuuu
on reset
State