MC68HC711P2CFN4 Freescale Semiconductor, MC68HC711P2CFN4 Datasheet - Page 218

• Manufacturer Part Number: MC68HC711P2CFN4
• Description: IC MCU 32K OTP 4MHZ 84-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711P2CFN4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Eeprom Size: 640 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

CPU Core and Instruction Set
11.3.6 Condition code register (CCR)
11.3.6.1 Carry/borrow (C)
11.3.6.2 Overflow (V)
11.3.6.3 Zero (Z)
11.3.6.4 Negative (N)
Technical Data
This 8-bit register contains five condition code indicators (C, V, Z, N, and
H), two interrupt masking bits, (IRQ and XIRQ) and a stop disable bit (S).
In the M68HC11 CPU, condition codes are automatically updated by
most instructions. For example, load accumulator A (LDAA) and store
accumulator A (STAA) instructions automatically set or clear the N, Z,
and V condition code flags. Pushes, pulls, add B to X (ABX), add B to Y
(ABY), and transfer/exchange instructions do not affect the condition
codes. Refer to
affected by a particular instruction.
The C-bit is set if the arithmetic logic unit (ALU) performs a carry or
borrow during an arithmetic operation. The C-bit also acts as an error
flag for multiply and divide operations. Shift and rotate instructions
operate with and through the carry bit to facilitate multiple-word shift
operations.
The overflow bit is set if an operation causes an arithmetic overflow.
Otherwise, the V-bit is cleared.
The Z-bit is set if the result of an arithmetic, logic, or data manipulation
operation is zero. Otherwise, the Z-bit is cleared. Compare instructions
do an internal implied subtraction and the condition codes, including Z,
reflect the results of that subtraction. A few operations (INX, DEX, INY,
and DEY) affect the Z-bit and no other condition flags. For these
operations, only ‘=’ and ‘¦’ conditions can be determined.
The N-bit is set if the result of an arithmetic, logic, or data manipulation
Freescale Semiconductor, Inc.
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CPU Core and Instruction Set
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Table
11-2, which shows the condition codes that are
MC68HC11P2 — Rev 1.0