MC68HC711P2CFN4 Freescale Semiconductor, MC68HC711P2CFN4 Datasheet - Page 170

• Manufacturer Part Number: MC68HC711P2CFN4
• Description: IC MCU 32K OTP 4MHZ 84-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711P2CFN4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Eeprom Size: 640 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Timing System
8.9.8 PWDTY1–4 — PWM timer duty cycle registers 1 to 4
Technical Data
Pulse width duty 1 (PWDTY1)
Pulse width duty 2 (PWDTY2)
Pulse width duty 3 (PWDTY3)
Pulse width duty 4 (PWDTY4)
NOTE:
There is one duty register for each channel. The value in this register
determines the duty cycle of the associated PWM timer channel.
PWDTYx is compared to the counter contents and if they are equal, a
match occurs and the output goes to the state defined by the associated
polarity bit. If the register is written while the channel is enabled, then the
new value is held in a buffer until the counter rolls over or the channel is
disabled. Reads of this register return the most recent value written.
If PWDTYx Š PWPERx then there will be no change of state due to the
duty cycle value. In addition, if the duty register is set to $00, then the
output will always be in the state which would normally be result from the
duty change of state (see also
PWMx
Freescale Semiconductor, Inc.
Address bit 7
For More Information On This Product,
$006C (bit 7)
$006D (bit 7)
$006E (bit 7)
$006F (bit 7)
Go to: www.freescale.com
Timing System
bit 6
PWDTYx
(6)
(6)
(6)
(6)
Figure 8-5. PWM duty cycle
bit 5
(5)
(5)
(5)
(5)
Boundary
bit 4
(4)
(4)
(4)
(4)
PWPERx
bit 3
(3)
(3)
(3)
(3)
cases).
bit 2
(2)
(2)
(2)
(2)
MC68HC11P2 — Rev 1.0
bit 1
(1)
(1)
(1)
(1)
(bit 0) 1111 1111
(bit 0) 1111 1111
(bit 0) 1111 1111
(bit 0) 1111 1111
bit 0
on reset
State