MC68HC711P2CFN4 Freescale Semiconductor, MC68HC711P2CFN4 Datasheet - Page 223
MC68HC711P2CFN4
Manufacturer Part Number
MC68HC711P2CFN4
Description
IC MCU 32K OTP 4MHZ 84-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheet
1.MC711P2CFNE4.pdf
(268 pages)
Specifications of MC68HC711P2CFN4
Core Processor
HC11
Core Size
8-Bit
Speed
4MHz
Connectivity
MI Bus, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
50
Program Memory Size
32KB (32K x 8)
Program Memory Type
OTP
Eeprom Size
640 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
84-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68HC711P2CFN4
Manufacturer:
MOT
Quantity:
5 510
Company:
Part Number:
MC68HC711P2CFN4
Manufacturer:
HITACHI
Quantity:
5 510
Company:
Part Number:
MC68HC711P2CFN4
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC68HC711P2CFN4
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
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11.7 Instruction set
MC68HC11P2 — Rev 1.0
ADCA (opr)
ADCB (opr)
ADDA (opr)
ADDB (opr)
ADDD (opr)
ANDA (opr)
Mnemonic
ABA
ABX
ABY
AND A with memory
Add with carry to A
Add with carry to B
Add accumulators
Add memory to A
Add memory to B
Add 16-bit to D
Add B to X
Add B to Y
Operation
Refer to
possible addressing modes. For each instruction, the table shows the
operand construction, the number of machine code bytes, and execution
time in CPU E clock cycles.
Table 11-2. Instruction set (Sheet 1 of 8)
Freescale Semiconductor, Inc.
For More Information On This Product,
Table
D + (M:M+1)
IX + (00:B)
IY + (00:B)
A + M + C
B + M + C
Description
A + M
B + M
A + B
A • M
CPU Core and Instruction Set
Go to: www.freescale.com
11-2, which shows all the M68HC11 instructions in all
A
A
A
B
A
B
IX
IY
D
A IMM
A DIR
A EXT
A IND, X
A IND, Y
B IMM
B DIR
B EXT
B IND, X
B IND, Y
A IMM
A DIR
A EXT
A IND, X
A IND, Y
B IMM
B DIR
B EXT
B IND, X
B IND, Y
A IMM
A DIR
A EXT
A IND, X
A IND, Y
Addressing
INH
INH
INH
IMM
DIR
EXT
IND, X
IND, Y
mode
Opcode
18 3A
18 A9
18 E9
18 AB
18 EB
18 E3
18 A4
1B
3A
89
99
B9
A9
C9
D9
F9
E9
8B
9B
BB
AB
CB
DB
FB
EB
C3
D3
F3
E3
84
94
B4
A4
Instruction
Operand
—
—
—
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
jj kk
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
CPU Core and Instruction Set
Cycles
2
3
4
2
3
4
4
5
2
3
4
4
5
2
3
4
4
5
2
3
4
4
5
4
5
6
6
7
2
3
4
4
5
— —
— — — — — — — —
— — — — — — — —
— —
— —
— —
— —
— — — —
— — — —
S X H I N Z V C
Condition codes
Technical Data
Instruction set
—
—
—
—
—
0 —
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