MC68HC711P2CFN4 Freescale Semiconductor, MC68HC711P2CFN4 Datasheet - Page 53

• Manufacturer Part Number: MC68HC711P2CFN4
• Description: IC MCU 32K OTP 4MHZ 84-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711P2CFN4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Eeprom Size: 640 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

3.5.2 Initialization
3.5.2.1 CONFIG — System configuration register
MC68HC11P2 — Rev 1.0
Configuration control (CONFIG) $003F
PSEL[4:0] — Priority select bits (refer to
Because bits in the following registers control the basic configuration of
the MCU, an accidental change of their values could cause serious
system problems. The protection mechanism, overridden in special
operating modes, requires a write to the protected bits only within the
first 64 bus cycles after any reset, or only once after each reset. See
Table
CONFIG controls the presence and/or location of ROM and EEPROM in
the memory map and enables the COP watchdog system. A security
feature that protects data in EEPROM and RAM is available on mask
programmed MCUs, controlled by the NOSEC bit. Refer to
EEPROM
CONFIG is made up of EEPROM cells and static working latches. The
operation of the MCU is controlled directly by these latches and not the
EEPROM byte. When programming the CONFIG register, the EEPROM
Freescale Semiconductor, Inc.
Address bit 7
For More Information On This Product,
3-3.
MODB
Operating Modes and On-Chip Memory
1
1
0
0
security.
Inputs
ROMA
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Table 3-4. Hardware mode select summary
D
MODA
0
1
0
1
bit 6
1
Special bootstrap
bit 5
Special test
Single chip
1
Expanded
Mode
PARE
bit 4
N
NOSE
Operating Modes and On-Chip Memory
bit 3
C
RBOOT
Resets and
Control bits in HPRIO
0
0
1
0
NOCO
bit 2
(latched at reset)
P
SMOD
ROMO
bit 1
0
0
1
1
N
Interrupts)
System initialization
EEON x11x 1xxx
bit 0
Technical Data
MDA
RAM and
0
1
0
1
on reset
State