MC68HC711P2CFN4 Freescale Semiconductor, MC68HC711P2CFN4 Datasheet - Page 237

• Manufacturer Part Number: MC68HC711P2CFN4
• Description: IC MCU 32K OTP 4MHZ 84-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711P2CFN4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Eeprom Size: 640 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Frequency of operation
E clock period
Crystal frequency
External oscillator frequency
Processor control set-up time
Reset input pulse width
Mode programming set-up time
Mode programming hold time
Interrupt pulse width (IRQ edge sensitive mode)
Timer pulse width
(Input capture and pulse accumulator inputs)
WAIT recovery start-up time
Clock monitor reset
PLL crystal frequency
PLL stabilization time
12.7 Control timing
MC68HC11P2 — Rev 1.0
1. All timing is given with respect to 20% and 70% of V
2. Reset is recognized during the first clock cycle it is held low. Internal circuitry then drives the pin low for four clock cycles,
3. To guarantee an external reset vector.
4. This is the minimum input time; it can be pre-empted by an internal reset.
releases the pin and samples the pin level two cycles later to determine the source of the interrupt. (See
rupts.)
Notes
(1) Rising edge sensitive input.
(2) Falling edge sensitive input.
(3) Maximum pulse accumulator clocking rate is E clock frequency divided by two (E/2).
Characteristic
PA[3:0]
PA[3:0]
PA7
PA7
(1), (3)
(2), (3)
(2)
(1)
(2)
(t
(1)
PCSU
(V
Freescale Semiconductor, Inc.
= t
DD
For More Information On This Product,
CYC
= 5.0 Vdc ± 10%, V
/4 + 50ns)
PW
Go to: www.freescale.com
TIM
Electrical Specifications
PW
PW
Symbol
PW
PW
f
DD
t
f
f
t
t
CMON
t
4f
t
t
PCSU
XTAL
WRS
XTAL
PLLS
MPH
f
CYC
RSTL
RSTL
MPS
OP
, unless otherwise noted.
OP
IRQ
TIM
(3)
(4)
SS
t
t
= 0 Vdc, T
CYC
CYC
Min.
500
175
10
10
—
—
—
—
2.0MHz
0
0
8
1
2
+20
+20
Max.
A
TBD
200
2.0
8.0
8.0
2.0
—
—
—
—
—
—
—
—
4
= T
L
t
t
to T
CYC
CYC
Min.
333
133
10
10
—
—
—
—
3.0MHz
0
0
8
1
2
H
+20
+20
)
Max.
12.0
12.0
TBD
200
3.0
2.0
—
—
—
—
—
—
—
—
4
Electrical Specifications
t
t
CYC
CYC
Min.
250
112
10
10
—
—
—
—
4.0MHz
0
0
8
1
2
Resets and Inter-
+20
+20
Technical Data
Control timing
Max.
TBD
16.0 MHz
16.0 MHz
200
4.0
2.0
—
—
—
—
—
—
—
—
4
MHz
t
t
t
MHz
Unit
kHz
CYC
CYC
CYC
ms
ns
ns
ns
ns
ns