MC68HC711P2CFN4 Freescale Semiconductor, MC68HC711P2CFN4 Datasheet - Page 142

• Manufacturer Part Number: MC68HC711P2CFN4
• Description: IC MCU 32K OTP 4MHZ 84-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711P2CFN4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Eeprom Size: 640 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Timing System
8.4 Input capture
Technical Data
The input capture function records the time an external event occurs by
latching the value of the free-running counter when a selected edge is
detected at the associated timer input pin. Software can store latched
values and use them to compute the periodicity and duration of events.
For example, by storing the times of successive edges of an incoming
signal, software can determine the period and pulse width of a signal. To
measure period, two successive edges of the same polarity are
captured. To measure pulse width, two alternate polarity edges are
captured.
In most cases, input capture edges are asynchronous with respect to the
internal timer counter, which is clocked relative to an internal clock
(PH2). These asynchronous capture requests are synchronized with
PH2 so that latching occurs on the opposite half cycle of PH2 from when
the timer counter is being incremented. This synchronization process
introduces a delay from when the edge occurs to when the counter value
is detected. Because these delays cancel out when the time between
two edges is being measured, the delay can be ignored. When an input
capture is being used with an output compare, there is a similar delay
between the actual compare point and when the output pin changes
state.
The control and status bits that implement the input capture functions
are contained in the PACTL, TCTL2, TMSK1, and TFLG1 registers.
To configure port A bit 3 as an input capture, clear the DDA3 bit of the
DDRA register. Note that this bit is cleared out of reset. To enable PA3
as the fourth input capture, set the I4/O5 bit in the PACTL register.
Otherwise, PA3 is configured as a fifth output compare out of reset, with
bit I4/O5 being cleared. If the DDA3 bit is set (configuring PA3 as an
output), and IC4 is enabled, then writes to PA3 cause edges on the pin
to result in input captures. Writing to TI4/O5 has no effect when the
TI4/O5 register is acting as IC4.
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Timing System
MC68HC11P2 — Rev 1.0