MC68HC711P2CFN4 Freescale Semiconductor, MC68HC711P2CFN4 Datasheet - Page 60

• Manufacturer Part Number: MC68HC711P2CFN4
• Description: IC MCU 32K OTP 4MHZ 84-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711P2CFN4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Eeprom Size: 640 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Operating Modes and On-Chip Memory
3.5.2.5 OPT2 — System configuration options register 2
Technical Data
System config. options 2 (OPT2) $0038 LIRDV CWOM
LIRDV — LIR driven
CWOM — Port C wired-OR mode
STRCH — Stretch external accesses
IRVNE — Internal read visibility/not E
Freescale Semiconductor, Inc.
In single chip and bootstrap modes, this bit has no meaning or effect.
The LIR pin is normally configured for wired-OR operation (only pulls
low). In order to detect consecutive instructions in a high-speed
application, this signal can be made to drive high for a quarter of a
cycle to prevent false triggering.
When this bit is set, off-chip accesses of addresses $0000–$7FFF
($8000–$FFFF, if ROMAD is clear) are extended by one E clock cycle
to allow access to slow peripherals. The E clock stretches externally,
but the internal clocks are not affected, so that timers and serial
systems are not corrupted. In single chip and boot modes this bit has
no effect.
IRVNE can be written once in any user mode. In expanded modes,
IRVNE determines whether IRV is on or off. In special test mode,
IRVNE is reset to one. In all other modes, IRVNE is reset to zero.
Address bit 7
For More Information On This Product,
1 = Enable LIR drive high pulse.
0 = LIR only driven low (requires pull-up on pin).
1 = Port C outputs are open-drain.
0 = Port C operates normally.
1 = Off-chip accesses are extended by one E clock cycle.
0 = Normal operation.
1 = Data from internal reads is driven out of the external data bus.
0 = No visibility of internal reads on external bus.
Operating Modes and On-Chip Memory
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bit 6
STRC
bit 5
H
IRVNE LSBF SPR2
bit 4
bit 3
bit 2
MC68HC11P2 — Rev 1.0
bit 1
0
bit 0
0
000x 0000
on reset
State