MC68HC711P2CFN4 Freescale Semiconductor, MC68HC711P2CFN4 Datasheet - Page 132

• Manufacturer Part Number: MC68HC711P2CFN4
• Description: IC MCU 32K OTP 4MHZ 84-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711P2CFN4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Eeprom Size: 640 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Serial Peripheral Interface (SPI)
7.7 SPI registers
7.7.1 SPCR — Serial peripheral control register
Technical Data
SPI control (SPCR)
The three SPI registers, SPCR, SPSR, and SPDR, provide control,
status, and data storage functions. Refer to the following information for
a description of how these registers are organized.
SPIE — Serial peripheral interrupt enable
SPE — Serial peripheral system enable
DWOM — Port D wired-OR mode
Freescale Semiconductor, Inc.
Set the SPIE bit to a one to request a hardware interrupt sequence
each time the SPIF or MODF status flag is set. SPI interrupts are
inhibited if this bit is clear or if the I bit in the condition code register is
one.
When the SPE bit is set, the port D pins 2, 3, 4, and 5 are dedicated
to the SPI functions and lose their general purpose I/O functions.
When the SPI system is enabled and expects any of PD[4:2] to be
inputs then those pins will be inputs regardless of the state of the
associated DDRD bits. If any of PD[4:2] are expected to be outputs
then those pins will be outputs only if the associated DDRD bits are
set. However, if the SPI is in the master mode, DDD5 determines
whether PD5 is an error detect input (DDD5 = 0) or a general-purpose
output (DDD5 = 1).
Address bit 7
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1 = A hardware interrupt sequence is requested each time SPIF or
0 = SPI interrupts are inhibited.
1 = Port D [5:2] is dedicated to the SPI.
0 = Port D has its default I/O functions.
1 = Port D [5:2] buffers configured for open-drain outputs.
0 = Port D [5:2] buffers configured for normal CMOS outputs.
MODF is set.
Serial Peripheral Interface (SPI)
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SPIE
bit 6
SPE DWOM MSTR CPOL CPHA SPR1 SPR0 0000 01uu
bit 5
bit 4
bit 3
bit 2
MC68HC11P2 — Rev 1.0
bit 1
bit 0
on reset
State