MC68HC711P2CFN4 Freescale Semiconductor, MC68HC711P2CFN4 Datasheet - Page 225

• Manufacturer Part Number: MC68HC711P2CFN4
• Description: IC MCU 32K OTP 4MHZ 84-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711P2CFN4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Eeprom Size: 640 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

MC68HC11P2 — Rev 1.0
BRCLR(opr)
BRSET(opr)
CMPA (opr)
CMPB (opr)
BSET (opr)
Mnemonic
COM (opr)
CPD (opr)
CLR (opr)
BRN (rel)
BSR (rel)
BVC (rel)
BVS (rel)
COMA
COMB
CLRA
CLRB
CBA
CLC
CLV
CLI
(msk)
(msk)
(msk)
(rel)
(rel)
Compare D with memory (16-bit)
Ones complement memory byte
Compare A with memory
Compare B with memory
Branch if overflow clear
Branch if overflow set
Branch to subroutine
Clear accumulator A
Clear accumulator B
Ones complement A
Ones complement B
Branch if bit(s) clear
Clear interrupt mask
Clear memory byte
Clear overflow flag
Branch if bit(s) set
Compare A with B
Clear carry bit
Branch never
Operation
Set bit(s)
Table 11-2. Instruction set (Sheet 3 of 8)
Freescale Semiconductor, Inc.
For More Information On This Product,
see
$FF – M
M + mm
$FF – A
$FF – B
M • mm = 0 ?
M • mm = 0 ?
Description
D – (M:M+1)
CPU Core and Instruction Set
Figure 11-2
1 = 0 ?
V = 0 ?
V = 1 ?
0
0
0
0
0
0
A – M
B – M
Go to: www.freescale.com
A – B
M
C
A
B
V
I
M
M
A
B
A INH
B INH
A IMM
A DIR
A EXT
A IND, X
A IND, Y
B IMM
B DIR
B EXT
B IND, X
B IND, Y
A INH
B INH
Addressing
DIR
IND, X
IND, Y
REL
DIR
IND, X
IND, Y
DIR
IND, X
IND, Y
REL
REL
REL
INH
INH
INH
DIR
IND, X
IND, Y
INH
EXT
IND, X
IND, Y
IMM
DIR
EXT
IND, X
IND, Y
mode
Opcode
18 1F
18 1E
18 1C
18 6F
18 A1
18 E1
18 63
1A 83
1A 93
1A B3
1A A3
CDA3
13
1F
21
12
1E
14
1C
8D
28
29
11
0C
0E
7F
6F
4F
5F
0A
81
91
B1
A1
C1
D1
F1
E1
73
63
43
53
Instruction
dd mm rr
ff mm rr
ff mm rr
dd mm rr
ff mm rr
ff mm rr
Operand
rr
dd mm
ff mm
ff mm
rr
rr
rr
—
—
—
hh ll
ff
ff
—
—
—
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
hh ll
ff
ff
—
—
jj kk
dd
hh ll
ff
ff
CPU Core and Instruction Set
Cycles
6
7
8
3
6
7
8
6
7
8
6
3
3
2
2
2
6
6
7
2
2
2
2
3
4
4
5
2
3
4
4
5
6
6
7
2
2
5
6
7
7
7
— — — — — — — —
— — — — — — — —
— — — — — — — —
— — — —
— — — — — — — —
— — — — — — — —
— — — — — — — —
— — — —
— — — — — — — 0
— — — 0 — — — —
— — — — 0 1 0 0
— — — — 0 1 0 0
— — — — 0 1 0 0
— — — — — — 0 —
— — — —
— — — —
— — — —
— — — —
— — — —
— — — —
S X H I N Z V C
Condition codes
Technical Data
Instruction set
0 —
0 1
0 1
0 1