MC68HC711P2CFN4 Freescale Semiconductor, MC68HC711P2CFN4 Datasheet - Page 126

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MC68HC711P2CFN4

Manufacturer Part Number
MC68HC711P2CFN4
Description
IC MCU 32K OTP 4MHZ 84-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheet

Specifications of MC68HC711P2CFN4

Core Processor
HC11
Core Size
8-Bit
Speed
4MHz
Connectivity
MI Bus, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
50
Program Memory Size
32KB (32K x 8)
Program Memory Type
OTP
Eeprom Size
640 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
84-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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Serial Peripheral Interface (SPI)
7.3 Functional description
7.4 SPI transfer formats
Technical Data
The central element in the SPI system is the block containing the shift
register and the read data buffer (see
buffered in the transmit direction and double buffered in the receive
direction. This means that new data for transmission cannot be written
to the shifter until the previous transfer is complete; however, received
data is transferred into a parallel read data buffer so the shifter is free to
accept a second serial character. As long as the first character is read
out of the read data buffer before the next serial character is ready to be
transferred, no overrun condition occurs. A single MCU register address
is used for reading data from the read data buffer and for writing data to
the shifter.
The SPI status block represents the SPI status functions (transfer
complete, write collision, and mode fault) performed by the serial
peripheral status register (SPSR). The SPI control block represents
those functions that control the SPI system through the serial peripheral
control register (SPCR).
During an SPI transfer, data is simultaneously transmitted and received.
A serial clock line synchronizes shifting and sampling of the information
on the two serial data lines. A slave select line allows individual selection
of a slave SPI device; slave devices that are not selected do not interfere
with SPI bus activities. On a master SPI device, the select line can
Freescale Semiconductor, Inc.
For More Information On This Product,
Serial Peripheral Interface (SPI)
Go to: www.freescale.com
PD2
PD3
PD4
PD5
Pin
Alternate
function
Figure
MISO
MOSI
SCK
SS
7-1). The system is single
MC68HC11P2 — Rev 1.0

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