MC68HC711P2CFN4 Freescale Semiconductor, MC68HC711P2CFN4 Datasheet - Page 147

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MC68HC711P2CFN4

Manufacturer Part Number
MC68HC711P2CFN4
Description
IC MCU 32K OTP 4MHZ 84-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheet

Specifications of MC68HC711P2CFN4

Core Processor
HC11
Core Size
8-Bit
Speed
4MHz
Connectivity
MI Bus, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
50
Program Memory Size
32KB (32K x 8)
Program Memory Type
OTP
Eeprom Size
640 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
84-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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8.5.1 TOC1–TOC4 — Timer output compare registers
MC68HC11P2 — Rev 1.0
Timer output compare 1 (TOC1)
Timer output compare 1 (TOC1)
Timer output compare 2 (TOC2)
Timer output compare 2 (TOC2)
Timer output compare 3 (TOC3)
Timer output compare 3 (TOC3)
Timer output compare 4 (TOC4)
Timer output compare 4 (TOC4)
high
high
high
high
low
low
low
low
All output compare registers are 16-bit read-write. Each is initialized to
$FFFF at reset. If an output compare register is not used for an output
compare function, it can be used as a storage location. A write to the
high-order byte of an output compare register pair inhibits the output
compare function for one bus cycle. This inhibition prevents
inappropriate subsequent comparisons. Coherency requires a complete
16-bit read or write. However, if coherency is not needed, byte accesses
can be used.
For output compare functions, write a comparison value to output
compare registers TOC1–TOC4 and TI4/O5. When TCNT value
matches the comparison value, specified pin actions occur.
All TOCx register pairs reset to ones ($FFFF).
Freescale Semiconductor, Inc.
Address bit 7
For More Information On This Product,
$001C (bit 15) (14)
$001D (bit 7)
$001A (bit 15) (14)
$001B (bit 7)
$0016 (bit 15) (14)
$0017 (bit 7)
$0018 (bit 15) (14)
$0019 (bit 7)
Go to: www.freescale.com
Timing System
bit 6
(6)
(6)
(6)
(6)
bit 5
(13)
(13)
(13)
(13)
(5)
(5)
(5)
(5)
bit 4
(12)
(12)
(12)
(12)
(4)
(4)
(4)
(4)
bit 3
(11)
(11)
(11)
(11)
(3)
(3)
(3)
(3)
bit 2
(10)
(10)
(10)
(10)
(2)
(2)
(2)
(2)
bit 1
(9)
(1)
(9)
(1)
(9)
(1)
(9)
(1)
(bit 8) 1111 1111
(bit 0) 1111 1111
(bit 8) 1111 1111
(bit 0) 1111 1111
(bit 8) 1111 1111
(bit 0) 1111 1111
(bit 8) 1111 1111
(bit 0) 1111 1111
bit 0
Output compare
Technical Data
Timing System
on reset
State

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