MC68HC711P2CFN4 Freescale Semiconductor, MC68HC711P2CFN4 Datasheet - Page 187

• Manufacturer Part Number: MC68HC711P2CFN4
• Description: IC MCU 32K OTP 4MHZ 84-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711P2CFN4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Eeprom Size: 640 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

10.3.4 COPRST — Arm/reset COP timer circuitry register
MC68HC11P2 — Rev 1.0
COP timer arm/reset (COPRST) $003A (bit 7)
The state of the NOCOP bit in the CONFIG register determines whether
the COP system is enabled or disabled. To change the enable status of
the COP system, change the contents of the CONFIG register and then
perform a system reset. In the special test and bootstrap operating
modes, the COP system is initially inhibited by the disable resets (DISR)
control bit in the TEST1 register. The DISR bit can subsequently be
written to zero to enable COP resets.
The COP timer rate control bits CR[1:0] in the OPTION register
determine the COP timeout period. The system E clock is divided by 2
and then further scaled by a factor shown in
these bits are zero, which selects the shortest timeout period. In normal
operating modes, these bits can only be written once within 64 bus
cycles after reset.
Complete the following reset sequence to service the COP timer. Write
$55 to COPRST to arm the COP timer clearing mechanism. Then write
$AA to COPRST to clear the COP timer. Executing instructions between
Freescale Semiconductor, Inc.
CR[1:0]
1. The timeout period has a tolerance of –0/+one cycle of the E/2
Address bit 7
For More Information On This Product,
0 0
0 1
1 0
1 1
asynchronous implementation of the COP circuitry. For example, with XTAL = 8MHz,
the uncertainty is –0/+16.384ms. See also the M68HC11 Reference Manual,
(M68HC11RM/AD).
E/2
Go to: www.freescale.com
Divide
E =
16
64
Resets and Interrupts
15
1
4
by
Table 10-1. COP timer rate select
bit 6
(6)
XTAL = 8MHz:
timeout
16.384 ms
65.536 ms
262.14 ms
1.049 sec
2.0 MHz
bit 5
(5)
(1)
bit 4
(4)
XTAL = 12MHz:
bit 3
(3)
10.923 ms
43.691 ms
174.76 ms
699.05 ms
timeout
3.0 MHz
Table
bit 2
(2)
(1)
10-1. After reset,
bit 1
(1)
Resets and Interrupts
15
XTAL = 16MHz:
clock due to the
(bit 0)
32.768 ms
131.07 ms
524.29 ms
timeout
8.192 ms
bit 0
4.0 MHz
Technical Data
on reset
affected
(1)
State
Resets
not
15