MC68HC711P2CFN4 Freescale Semiconductor, MC68HC711P2CFN4 Datasheet - Page 61

• Manufacturer Part Number: MC68HC711P2CFN4
• Description: IC MCU 32K OTP 4MHZ 84-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711P2CFN4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Eeprom Size: 640 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

3.5.2.6 BPROT — Block protect register
MC68HC11P2 — Rev 1.0
Block protect (BPROT)
LSBF — LSB-first enable (refer to
SPR2 — SPI clock rate select (refer to
(SPI))
Bits 1, 0 — not implemented; always read zero.
BPROT prevents accidental writes to EEPROM and the CONFIG
register. The bits in this register can be written to zero only once during
the first 64 E clock cycles after reset in the normal modes; they can be
set at any time. Once the bits are cleared, the EEPROM array and the
CONFIG register can be programmed or erased. Setting the bits in the
BPROT register to logic one protects the EEPROM and CONFIG
Special test
Single chip
Expanded
Freescale Semiconductor, Inc.
In single chip modes this bit determines whether the E clock drives
out from the chip.
Refer to the following table for a summary of the operation
immediately following reset.
This bit adds a divide-by-four to the SPI clock chain.
Mode
Boot
Address bit 7
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1 = E pin is driven low.
0 = E clock is driven out from the chip.
1 = Data is transferred LSB first.
0 = Data is transferred MSB first.
Operating Modes and On-Chip Memory
after reset
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IRVNE
0
0
0
1
bit 6
0
after reset
BPRT4
E clock
bit 5
On
On
On
On
PTCO
bit 4
N
Serial Peripheral Interface
after reset
Table 3-7
BPRT3 BPRT2 BPRT1 BPRT0 1011 1111
Operating Modes and On-Chip Memory
IRV
bit 3
On
Off
Off
Off
Serial Peripheral Interface
bit 2
affects only
IRVNE
IRV
IRV
E
E
bit 1
System initialization
bit 0
can be written
Technical Data
Unlimited
IRVNE
Once
Once
Once
(SPI))
on reset
State