MC68HC711P2CFN4 Freescale Semiconductor, MC68HC711P2CFN4 Datasheet - Page 200

• Manufacturer Part Number: MC68HC711P2CFN4
• Description: IC MCU 32K OTP 4MHZ 84-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711P2CFN4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Eeprom Size: 640 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Resets and Interrupts
10.6 Interrupts
10.6.1 Interrupt recognition and register stacking
Technical Data
Excluding reset type interrupts, the MC68HC11P2 has 20 interrupt
vectors that support 32 interrupt sources. The 17 maskable interrupts
are generated by on-chip peripheral systems. These interrupts are
recognized when the global interrupt mask bit (I) in the condition code
register (CCR) is clear. The three nonmaskable interrupt sources are
illegal opcode trap, software interrupt, and XIRQ pin. Refer to
4, which shows the interrupt sources and vector assignments for each
source.
For some interrupt sources, such as the SCI interrupts, the flags are
automatically cleared during the normal course of responding to the
interrupt requests. For example, the RDRF flag in the SCI system is
cleared by the automatic clearing mechanism consisting of a read of the
SCI status register while RDRF is set, followed by a read of the SCI data
register. The normal response to an RDRF interrupt request would be to
read the SCI status register to check for receive errors, then to read the
received data from the SCI data register. These two steps satisfy the
automatic clearing mechanism without requiring any special
instructions.
An interrupt can be recognized at any time after it is enabled by its local
mask, if any, and by the global mask bit in the CCR. Once an interrupt
source is recognized, the CPU responds at the completion of the
instruction being executed. Interrupt latency varies according to the
number of cycles required to complete the current instruction. When the
CPU begins to service an interrupt, the contents of the CPU registers are
pushed onto the stack in the order shown in
value is stacked, the I-bit and the X-bit, if XIRQ is pending, are set to
inhibit further interrupts. The interrupt vector for the highest priority
pending source is fetched, and execution continues at the address
specified by the vector. At the end of the interrupt service routine, the
return from interrupt instruction is executed and the saved registers are
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Resets and Interrupts
Table
MC68HC11P2 — Rev 1.0
10-5. After the CCR
Table 10-