MC68HC711P2CFN4 Freescale Semiconductor, MC68HC711P2CFN4 Datasheet - Page 27

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MC68HC711P2CFN4

Manufacturer Part Number
MC68HC711P2CFN4
Description
IC MCU 32K OTP 4MHZ 84-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheet

Specifications of MC68HC711P2CFN4

Core Processor
HC11
Core Size
8-Bit
Speed
4MHz
Connectivity
MI Bus, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
50
Program Memory Size
32KB (32K x 8)
Program Memory Type
OTP
Eeprom Size
640 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
84-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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2.7.1 Synchronization of PLL with subsystems
MC68HC11P2 — Rev 1.0
EXTAL
Low frequency
crystal oscillator
t
REF
Phase
detect
The PLL filter has two bandwidths that are automatically selected by the
PLL, if the AUTO bit in PLLCR is set. Whenever the PLL is first enabled,
the wide bandwidth mode is used. This enables the PLL frequency to
ramp up quickly. When the output frequency is near the desired value,
the filter is switched to the narrow bandwidth mode, to make the final
frequency more stable. Manual control is possible, by clearing AUTO in
PLLCR, and setting the appropriate value for BWC.
A block diagram of the PLL circuitry is given in
The timer and SCI subsystems operate off the EXTAL clock, but are
accessed by the CPU relative to the internal PH2 signal. Although the
EXTAL clock is used as the reference for the PLL, the PH2 clock and the
module clocks for the timer and the SCI are not synchronized. In order
t
PCOMP
FB
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure 2-4. PLL circuit
Frequency divider
Go to: www.freescale.com
Loop filter
SYNR
Pin Descriptions
V
DDSYN
XFC
VCO
VCOOUT
EXTAL
Phase-locked loop (XFC, VDDSYN)
EXTAL
Bus clock
Figure
select
BCS
Module clock
select
MCS
2-4.
Pin Descriptions
Technical Data
4XCLK
To clock
generation
circuitry
ST4XCK
For SCI
and timer

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