MC68HC711P2CFN4 Freescale Semiconductor, MC68HC711P2CFN4 Datasheet - Page 219

• Manufacturer Part Number: MC68HC711P2CFN4
• Description: IC MCU 32K OTP 4MHZ 84-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711P2CFN4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Eeprom Size: 640 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

11.3.6.5 Interrupt mask (I)
11.3.6.6 Half carry (H)
11.3.6.7 X interrupt mask (X)
MC68HC11P2 — Rev 1.0
to test whether the contents of a memory location have the MSB set is
to load it into an accumulator and then check the status of the N-bit.
The interrupt request (IRQ) mask (I-bit) is a global mask that disables all
maskable interrupt sources. While the I-bit is set, interrupts can become
pending, but the operation of the CPU continues uninterrupted until the
I-bit is cleared. After any reset, the I-bit is set by default and can only be
cleared by a software instruction. When an interrupt is recognized, the
I-bit is set after the registers are stacked, but before the interrupt vector
is fetched. After the interrupt has been serviced, a return from interrupt
instruction is normally executed, restoring the registers to the values that
were present before the interrupt occurred. Normally, the I-bit is zero
after a return from interrupt is executed. Although the I-bit can be cleared
within an interrupt service routine, ‘nesting’ interrupts in this way should
only be done when there is a clear understanding of latency and of the
arbitration mechanism. Refer to
The H-bit is set when a carry occurs between bits 3 and 4 of the
arithmetic logic unit during an ADD, ABA, or ADC instruction. Otherwise,
the H-bit is cleared. Half carry is used during BCD operations.
The XIRQ mask (X) bit disables interrupts from the XIRQ pin. After any
reset, X is set by default and must be cleared by a software instruction.
When an XIRQ interrupt is recognized, the X and I bits are set after the
registers are stacked, but before the interrupt vector is fetched. After the
interrupt has been serviced, an RTI instruction is normally executed,
causing the registers to be restored to the values that were present
before the interrupt occurred. The X interrupt mask bit is set only by
hardware (RESET or XIRQ acknowledge). X is cleared only by program
instruction (TAP, where the associated bit of A is 0; or RTI, where bit 6
Freescale Semiconductor, Inc.
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CPU Core and Instruction Set
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Resets and
Interrupts.
CPU Core and Instruction Set
Technical Data
Registers