MC68HC711P2CFN4 Freescale Semiconductor, MC68HC711P2CFN4 Datasheet - Page 157

• Manufacturer Part Number: MC68HC711P2CFN4
• Description: IC MCU 32K OTP 4MHZ 84-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711P2CFN4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Eeprom Size: 640 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

8.6.3 PACTL — Pulse accumulator control register
8.7 Computer operating properly watchdog function
MC68HC11P2 — Rev 1.0
Pulse accumulator control
(PACTL)
Bits RTR[1:0] of this register select the rate for the RTI system. The
remaining bits control the pulse accumulator and IC4/OC5 functions.
Bits 7, 3 — Not implemented; always read zero
PAEN — Pulse accumulator system enable (refer to
accumulator)
PAMOD — Pulse accumulator mode (refer to
PEDGE — Pulse accumulator edge control (refer to
accumulator)
I4/O5 — Input capture 4/output compare (refer to
accumulator)
RTR[1:0] — RTI interrupt rate select
The clocking chain for the COP function, tapped off from the main timer
divider chain, is only superficially related to the main timer system. The
CR[1:0] bits in the OPTION register and the NOCOP bit in the CONFIG
register determine the status of the COP function. One additional
register, COPRST, is used to arm and clear the COP watchdog reset
system. Refer to
of the COP function.
Freescale Semiconductor, Inc.
These two bits determine the rate at which the RTI system requests
interrupts. The RTI system is driven by an E/2
compensated so it is independent of the timer prescaler. These two
control bits select an additional division factor. Refer to
Address bit 7
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0
Resets and Interrupts
Timing System
PAEN PAMODPEDGE
bit 6
bit 5
Computer operating properly watchdog function
bit 4
bit 3
0
for a more detailed discussion
I4/O5 RTR1 RTR0 0000 0000
bit 2
Pulse
13
bit 1
clock rate that is
Pulse
accumulator)
Pulse
Pulse
bit 0
Table
Technical Data
Timing System
on reset
8-2.
State