n25q256 Numonyx, n25q256 Datasheet - Page 100

• Manufacturer Part Number: n25q256
• Description: 256-mbit 3 V, Multiple I/o, 4-kbyte Subsector Erase, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
• Manufacturer: Numonyx

Instructions
9.1.32
100/186
S
C
DQ0
Write to Lock Register (WRLR)
The Write to Lock Register (WRLR) instruction allows bits to be changed in the Lock
Registers. Before it can be accepted, a Write Enable (WREN) instruction must previously
have been executed. After the Write Enable (WREN) instruction has been decoded, the
device sets the Write Enable Latch (WEL).
The Write to Lock Register (WRLR) instruction is entered by driving Chip Select (S) Low,
followed by the instruction code, three address bytes (pointing to any address in the
targeted sector and one data byte on Serial Data input (DQ0). Chip Select (S) must be
driven High after the eighth bit of the data byte has been latched in, otherwise the Write to
Lock Register (WRLR) instruction is not executed.
Lock Register bits are volatile, and therefore do not require time to be written. When the
Write to Lock Register (WRLR) instruction has been successfully executed, the Write
Enable Latch (WEL) bit is reset after a delay time less than tSHSL minimum value.
Any Write to Lock Register (WRLR) instruction, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle that is in progress. If 4-byte
address mode is enabled, the device uses a 32-bit address as explained and shown in
Section 5.1.2: 4 Byte Address Mode on page 25
Figure 48. Write to Lock Register instruction sequence
Table 23.
1. Values of (b1, b0) after power-up are defined in
All sectors
0
Sector
1
Lock Register in
2
Instruction
3
4
5
6
b7-b2
Bit
7
b1
b0
MSB
23
8
(1)
22 21
9 10
Sector Lock Down bit value (refer to
Sector Write Lock bit value (refer to
24-Bit Address
Micron Technology, Inc., reserves the right to change products or specifications without notice.
3
28 29 30 31 32 33 34 35
Section 7: Protection
2
1
0
MSB
7
6
5
Lock Register
modes.
4
Value
In
‘0’
3
36 37 38
©2010 Micron Technology, Inc. All rights reserved.
2
Table
Table
1
0
39
22)
22)
N25Q256 - 3 V