n25q256 Numonyx, n25q256 Datasheet - Page 121

• Manufacturer Part Number: n25q256
• Description: 256-mbit 3 V, Multiple I/o, 4-kbyte Subsector Erase, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
• Manufacturer: Numonyx

N25Q256 - 3 V
9.2.10
9.2.11
DQ0
DQ1
C
Subsector Erase (SSE)
The Subsector Erase (SSE) instruction sets to '1' (FFh) all bits inside the chosen subsector.
Before it can be accepted, a Write Enable (WREN) instruction must have been executed
previously.
Apart form parallelizing the instruction code and the address on pins DQ0 and DQ1, the
instruction functionality is the same as the Subsector Erase (SSE) instruction of the
Extended SPI protocol; Refer to
If 4-byte address mode is enabled, the device uses a 32-bit address as explained and
shown in
Figure 73. Subsector Erase instruction sequence DIO-SPI
S
Sector Erase (SE)
The Sector Erase (SE) instruction sets to '1' (FFh) all bits inside the chosen sector. Before it
can be accepted, a Write Enable (WREN) instruction must previously have been executed.
Apart form parallelizing the instruction code and the address on the two pins DQ0 and DQ1,
the instruction functionality is the same as the Sector Erase (SE) instruction of the Extended
SPI protocol, please refer to
If 4-byte address mode is enabled, the device uses a 32-bit address as explained and
shown in
Section 5.1.2: 4 Byte Address Mode on page 25
Section 5.1.2: 4 Byte Address Mode on page 25
0
Instruction
1
2
3
Section 9.1.25: Sector Erase (SE)
23 21 19 17
22 20 18 16
4
Section 9.1.24: Subsector Erase (SSE)
5
6
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
24-bit Address
15 13 11 9
14 12 10 8
8
9 10 11
12 13 14 15
7
6
5
4
3
2
for further details.
©2010 Micron Technology, Inc. All rights reserved.
1
0
for further details.
Instructions
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