n25q256 Numonyx, n25q256 Datasheet - Page 81

• Manufacturer Part Number: n25q256
• Description: 256-mbit 3 V, Multiple I/o, 4-kbyte Subsector Erase, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
• Manufacturer: Numonyx

N25Q256 - 3 V
9.1.16
Write Enable (WREN)
The Write Enable (WREN) instruction sets the Write Enable Latch (WEL) bit.
The Write Enable Latch (WEL) bit must be set prior to every Program, Erase, or Write
instruction:
Page Program (PP), Dual Input Fast Program (DIFP), Dual Input Extended Fast Program
(DIEFP), Quad Input Fast Program (QIFP), Quad Input Extended Fast Program (QIEFP),
Program OTP (POTP), Write to Lock Register (WRLR), Subsector Erase (SSE), Sector
Erase (SE), Bulk Erase (BE), Write Status Register (WRSR), Write Configuration Register
(WRCR), Write Enhanced Configuration Register (WRECR), and Write Extended Address
Register (WREAR), Enter 4-byte address mode (EN4BYTEADDR), Exit 4-byte address
mode (EX4BYTEADDR), and Write NV Configuration Register (WRNVCR) instruction.
The Write Enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the
instruction code, and then driving Chip Select (S) High.
At the end of the POR sequence the WEL bit is low, so the next modify instruction can be
accepted.
Figure 33. Write Enable instruction sequence
S
C
DQ0
DQ1
High Impedance
0
1
2
Instruction
3
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AI13731
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