n25q256 Numonyx, n25q256 Datasheet - Page 85

• Manufacturer Part Number: n25q256
• Description: 256-mbit 3 V, Multiple I/o, 4-kbyte Subsector Erase, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
• Manufacturer: Numonyx

N25Q256 - 3 V
As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose
duration is top) is initiated. While the Dual Input Fast Program (DIFP) cycle is in progress,
the Status Register and the Flag Status Register may be read to check if the internal modify
cycle is finished. At some unspecified time before the cycle is completed, the Write Enable
Latch (WEL) bit is reset.
A Dual Input Fast Program (DIFP) instruction applied to a page that is protected by the
Block Protect (BP3, BP2, BP1, BP0 and TB) bits is not executed.
Dual Input Fast Program cycle can be paused by mean of Program/Erase Suspend (PES)
instruction and resumed by mean of Program/Erase Resume (PER) instruction.
If 4-byte address mode is enabled, the device uses a 32-bit address as explained and
shown in
Figure 36. Dual Input Fast Program instruction sequence
S
C
DQ0
DQ1
S
C
DQ0
DQ1
Section 5.1.2: 4 Byte Address Mode on page 25
MSB
6
7
32
DATA IN 1
0
4
5
33
1
2
3
34
2
Instruction
0
1
35 36 37 38 39 40 41 42
MSB
3
6
7 5
DATA IN 2
4
4
5
3
2
High Impedance
6
0
1
7
MSB
6
7 5
DATA IN 3
23
8
4
22 21
9 10
2
3
24-bit Address
Micron Technology, Inc., reserves the right to change products or specifications without notice.
0
1
43
MSB
6
7 5
44 45 46 47
DATA IN 4
3
28 29 30 31
4
2
2
3
1
0
1
0
MSB
6
7
DATA IN 5
4
5
2
3
0
1
©2010 Micron Technology, Inc. All rights reserved.
MSB
6
DATA IN 256
7
4
5
2
3
0
1
Instructions
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