n25q256 Numonyx, n25q256 Datasheet - Page 101

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n25q256

Manufacturer Part Number
n25q256
Description
256-mbit 3 V, Multiple I/o, 4-kbyte Subsector Erase, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
Manufacturer
Numonyx
Datasheet

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N25Q256 - 3 V
9.1.33
9.1.34
S
C
DQ0
DQ1
Read Flag Status Register
The Read Flag Status Register (RFSR) instruction allows the Flag Status Register to be
read. The Status Register may be read at any time, even while a Program, Erase. When one
of these cycles is in progress, it is recommended to check the P/E Controller bit (Not WIP)
bit before sending a new instruction to the device. It is also possible to read the Flag
Register continuously, as shown here.
Figure 49. Read Flag Status Register instruction sequence
Clear Flag Status Register
The Clear Flag Status Register (CLFSR) instruction reset the error Flag Status Register bits
(Erase Error bit, Program Error bit, VPP Error bit, Protection Error bit). It is not necessary to
set the WEL bit before the Clear Flag Status Register instruction is executed. The WEL bit
will be unchanged after this command is executed.
Figure 50. Clear Flag Status Register instruction sequence
S
C
DQ0
DQ1
0
High Impedance
1
2
Instruction
3
0
4
1
High Impedance
5
2
Instruction
6
3
7
4
7
8
5
Flag Status Register Out
6
9 10 11 12 13 14 15
6
5
7
MSB
MSB
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
8
3
2
1
0
7
Flag Status Register Out
6
5
©2010 Micron Technology, Inc. All rights reserved.
MSB
4
3
2
1
0
Instructions
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