n25q256 Numonyx, n25q256 Datasheet - Page 137

• Manufacturer Part Number: n25q256
• Description: 256-mbit 3 V, Multiple I/o, 4-kbyte Subsector Erase, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
• Manufacturer: Numonyx

N25Q256 - 3 V
9.3.2
Note:
9.3.3
DQ0
DQ1
DQ3
DQ2
C
S
Mode 3
Mode 0
Read Serial Flash Discovery Parameter
The Read Serial Flash Discovery Parameter (RDSFDP) instruction allows reading the Serial
Flash Discovery Parameter area (SFDP) in the QIO-SPI protocol. The instruction
functionality is exactly the same as the Read Serial Flash Discovery Parameter instruction
of the Extended SPI protocol. The only difference is that in the QIO-SPI protocol instruction
code, address and output data are all parallelized on the four pins DQ0, DQ1, DQ2 and
DQ3.
The serial flash discovery parameter area is always addressable by means 3 byte
regardless active address mode.
The dummy byte bits can not be parallelized: 8 clock cycles are requested to perform the
internal reading operation.
Figure 96. Quad Read Serial Flash Discovery Parameter
Quad Command Fast Read (QCFR)
The Quad Command Fast Read (QCFR) instruction allows to read the memory in QIO-SPI
protocol, parallelizing the instruction code, the address and the output data on four pins
(DQ0, DQ1, DQ2 and DQ3). The Quad Command Fast Read (QCFR) instruction can be
issued, after the device is set in QIO-SPI mode, by sending to the memory indifferently one
of the 3 instructions codes: 0Bh, 6Bh or EBh, the effect is exactly the same. The 3
instruction codes are all accepted to help the application code porting from Extended SPI
protocol to QIO-SPI protocol.
Apart for the parallelizing on four pins of the instruction code, the Quad Command Fast
Read instruction functionality is exactly the same as the Quad I/O Fast Read of the
Extended SPI protocol, please refer to
details.
If 4-byte address mode is enabled, the device uses a 32-bit address as explained and
shown in
Instruction
0
Section 5.1.2: 4 Byte Address Mode on page 25
1
21 17 13 9
20 16 12 8
22 18 14 10 6
23 19 15 11 7
2
24 bit Address
3
4
5
5
4
6
1
0
2
3
7
8
9 10
Section 9.1.13: Quad I/O Fast Read
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Dummy
13 14 15 16
Byte 1 Byte 2
IO switches from Input to Output
5
4
6
7
1
17
0
3
2
18
5
4
7
6
19
0
1
3
2
20
4
Byte 3 Byte 4
5
7
6
©2010 Micron Technology, Inc. All rights reserved.
21
0
1
3
2
22
4
5
7
6
23 24 25
0
1
3
2
4
4
4
Byte 5 Byte 6
4
for further
0
0
0
0
Instructions
4
4
4
4
0
0
0
0
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