n25q256 Numonyx, n25q256 Datasheet - Page 127

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n25q256

Manufacturer Part Number
n25q256
Description
256-mbit 3 V, Multiple I/o, 4-kbyte Subsector Erase, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
Manufacturer
Numonyx
Datasheet

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N25Q256 - 3 V
9.2.21
9.2.22
Read NV Configuration Register, Dual I/O
The Read Non Volatile Configuration Register (RDNVCR) instruction allows the Non Volatile
Configuration Register to be read.
Figure 84. Read NV Configuration Register instruction sequence DIO-SPI
Write NV Configuration Register, Dual I/O
The Write Non Volatile Configuration register (WRNVCR) instruction allows new values to
be written to the Non Volatile Configuration register. Before it can be accepted, a write
enable (WREN) instruction must previously have been executed.
Apart form the parallelizing of the instruction code and the input data on the two pins DQ0
and DQ1, the instruction functionality is exactly the same as the Write Non Volatile
Configuration Register (WNVCR) instruction of the Extended SPI protocol, please refer to
Section 9.1.36: Write NV Configuration Register
Figure 85. Write NV Configuration Register instruction sequence DIO-SPI
DQ0
DQ1
C
S
DQ0
DQ1
C
S
0
Instruction
0
1
Instruction
1
2
2
3
3
7
6
4
7
6
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
LS Byte
5
4
5
Byte
LS Byte
5
4
5
Byte
3
2
6
3
2
6
NVCR Out
1
0
NVCR In
7
1
0
7
for further details.
15 13 11 9
14 12 10 8
15 13 11 9
14 12 10 8
8
8
MS Byte
MS Byte
9 10 11
9 10 11
Byte
Byte
©2010 Micron Technology, Inc. All rights reserved.
Instructions
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